On 7/14/2026 4:09 PM, Mitul Golani wrote:
Split the CMRR M/N register programming into intel_vrr_enable_cmrr()
and intel_vrr_disable_cmrr(), and drive them from
intel_vrr_set_transcoder_timings() based on crtc_state->cmrr.enable.
crtc_state->vrr.cmrr.enable
VRR_CTL_CMRR_ENABLE is not set explicitly, writing TRANS_CMRR_N_HI
arms CMRR in hardware. Drop the now-unused cmrr_enable
argument to intel_vrr_tg_enable().
No functional change intended for non-CMRR configurations.
--v2:
- Commit message changes.
- Added Simplified enable/disable sequence. (Chaitanya)
Signed-off-by: Mitul Golani <[email protected]>
Assisted-by: Claude:claude-opus-4-8
---
drivers/gpu/drm/i915/display/intel_vrr.c | 51 ++++++++++++++++++++----
1 file changed, 43 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 95c7b0c05ec3..52fe40fdbdb3 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -624,6 +624,34 @@ static u32 trans_vrr_ctl(const struct intel_crtc_state
*crtc_state)
VRR_CTL_PIPELINE_FULL_OVERRIDE;
}
+static void
+intel_vrr_enable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder),
+ upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+ intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder),
+ lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+ intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder),
+ lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+ intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder),
+ upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+}
+
+static void
+intel_vrr_disable_cmrr(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+ enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
+
+ intel_de_write(display, TRANS_CMRR_M_HI(display, cpu_transcoder), 0);
+ intel_de_write(display, TRANS_CMRR_M_LO(display, cpu_transcoder), 0);
+ intel_de_write(display, TRANS_CMRR_N_HI(display, cpu_transcoder), 0);
+ intel_de_write(display, TRANS_CMRR_N_LO(display, cpu_transcoder), 0);
TRANS_CMRR_N_HI should be the last register to be written.
+}
+
void intel_vrr_set_transcoder_timings(const struct intel_crtc_state
*crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
@@ -662,6 +690,13 @@ void intel_vrr_set_transcoder_timings(const struct
intel_crtc_state *crtc_state)
intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
intel_cmtg_set_vrr_timings(crtc_state);
+ if (HAS_CMRR(display)) {
+ if (crtc_state->vrr.cmrr.enable)
+ intel_vrr_enable_cmrr(crtc_state);
+ else
+ intel_vrr_disable_cmrr(crtc_state);
+ }
+
CMRR M/N now gets written twice. intel_vrr_set_transcoder_timings()
calls intel_vrr_set_fixed_rr_timings() and then also calls
intel_vrr_enable_cmrr(). Same values, so no functional breakage, but
it's redundant
if (!intel_vrr_always_use_vrr_tg(display))
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
trans_vrr_ctl(crtc_state));
@@ -924,8 +959,7 @@ intel_vrr_disable_dc_balancing(const struct
intel_crtc_state *old_crtc_state)
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
vrr_ctl);
}
-static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
- bool cmrr_enable)
+static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -937,11 +971,12 @@ static void intel_vrr_tg_enable(const struct
intel_crtc_state *crtc_state,
vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
/*
- * FIXME this might be broken as bspec seems to imply that
- * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
- * when enabling CMRR (but not when disabling CMRR?).
+ * This full TRANS_VRR_CTL write is the authoritative one, so it must
+ * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing
TRANS_CMRR_N_HI
+ * arms the bit in hardware, but this later write would otherwise clear
+ * it again.
*/
- if (cmrr_enable)
+ if (crtc_state->vrr.cmrr.enable)
vrr_ctl |= VRR_CTL_CMRR_ENABLE;
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
@@ -977,7 +1012,7 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
intel_vrr_enable_dc_balancing(crtc_state);
if (!intel_vrr_always_use_vrr_tg(display))
- intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
+ intel_vrr_tg_enable(crtc_state);
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1004,7 +1039,7 @@ void intel_vrr_transcoder_enable(const struct
intel_crtc_state *crtc_state)
return;
if (intel_vrr_always_use_vrr_tg(display))
- intel_vrr_tg_enable(crtc_state, false);
+ intel_vrr_tg_enable(crtc_state);
}
void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)
