Wa_16030862157:
Interpret 0xF populated-channel count as 16
The register MEM_SS_INFO_GLOBAL [Number of populated channels] field
definition is updated with an encoding for 16 channels.
For 16-channel configuration, program 1111b. A programmed value of 1111b
must be interpreted as 16 channels for memory bandwidth calculations.
The MEM_SS_INFO_GLOBAL populated-channel field is only 4 bits and cannot
encode 16, so on Xe3p the BIOS programs the saturated field value (0xf)
to indicate the fully-populated 16-channel config (4 memory controllers
x 4 channels). Interpret it as 16 and let the bandwidth math handle the
larger channel count.
v2: Limit the WA only till NVL (Suraj)
Logical separation of WA (Vinod)
WA: 16030862157, 16030875223
Bspec: 69131, 79482
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Uma Shankar <[email protected]>
---
drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++
drivers/gpu/drm/i915/display/intel_display_wa.h | 1 +
drivers/gpu/drm/i915/display/intel_dram.c | 14 +++++++++++++-
3 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c
b/drivers/gpu/drm/i915/display/intel_display_wa.c
index b4c49816f7eb..3662e0f17c69 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.c
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -140,6 +140,8 @@ bool __intel_display_wa(struct intel_display *display, enum
intel_display_wa wa,
STEP_A0, STEP_B0);
case INTEL_DISPLAY_WA_16029024088:
return DISPLAY_VER(display) >= 35;
+ case INTEL_DISPLAY_WA_16030862157:
+ return DISPLAY_VER(display) == 35;
case INTEL_DISPLAY_WA_18034343758:
return DISPLAY_VER(display) == 20 ||
(display->platform.pantherlake &&
diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h
b/drivers/gpu/drm/i915/display/intel_display_wa.h
index 92b3980bea84..338b32e4162d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_wa.h
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -54,6 +54,7 @@ enum intel_display_wa {
INTEL_DISPLAY_WA_16025573575,
INTEL_DISPLAY_WA_16025596647,
INTEL_DISPLAY_WA_16029024088,
+ INTEL_DISPLAY_WA_16030862157,
INTEL_DISPLAY_WA_18034343758,
INTEL_DISPLAY_WA_22010178259,
INTEL_DISPLAY_WA_22010947358,
diff --git a/drivers/gpu/drm/i915/display/intel_dram.c
b/drivers/gpu/drm/i915/display/intel_dram.c
index f103f7cba018..0763d0bfd98e 100644
--- a/drivers/gpu/drm/i915/display/intel_dram.c
+++ b/drivers/gpu/drm/i915/display/intel_dram.c
@@ -13,6 +13,7 @@
#include "intel_display_core.h"
#include "intel_display_utils.h"
#include "intel_display_regs.h"
+#include "intel_display_wa.h"
#include "intel_dram.h"
#include "intel_mchbar.h"
#include "intel_parent.h"
@@ -794,7 +795,18 @@ static int xelpdp_get_dram_info(struct intel_display
*display, struct dram_info
dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK,
val);
dram_info->num_qgv_points =
REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
- /* PSF GV points not supported in D14+ */
+
+ /*
+ * Wa_16030862157
+ * MEM_SS_INFO_GLOBAL populated-channel field is only 4 bits and
+ * cannot encode 16, so on Xe3p the BIOS programs the saturated field
+ * value (0xf) to indicate the fully-populated 16-channel config (4
+ * memory controllers x 4 channels). Interpret it as 16.
+ */
+
+ if (intel_display_wa(display, INTEL_DISPLAY_WA_16030862157) &&
+ dram_info->num_channels ==
REG_FIELD_MAX(MTL_N_OF_POPULATED_CH_MASK))
+ dram_info->num_channels = 16;
if (DISPLAY_VER(display) >= 35)
dram_info->ecc_impacting_de_bw =
REG_FIELD_GET(XE3P_ECC_IMPACTING_DE, val);
--
2.50.1
