On Fri, Jul 17, 2026 at 06:51:06PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <[email protected]>
>
> Apparently PTL+ no longer has the cd2x pipe select field in
> CDCLK_CTL. Take that into account during CDCLK sanitization.
>
> This currently triggers a spurious CDCLK sanitization during
> driver load on PTL+ which will causes a visible glitch on all
> active displays.
>
> Cc: [email protected]
> Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/work_items/8550
> Fixes: 3f9de66f8acb ("drm/i915/cdclk: Fix up CDCLK_FREQ_DECIMAL without a
> full PLL re-enable")
> Signed-off-by: Ville Syrjälä <[email protected]>
> ---
Unfortunately the regression itself has a cc:stable on it, so we'll
need to backport this fix as well.
To do that cleanly we need to pick up these as well:
commit cd16e794aead ("drm/i915/cdclk: Clean up CDCLK_CTL defines")
commit 67d77d9472c6 ("drm/i915/cdclk: Introduce bxt_cdclk_cd2x_pipe_mask() and
use it")
> drivers/gpu/drm/i915/display/intel_cdclk.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c
> b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index a53d88727177..9e5e15b0c4d1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -2381,8 +2381,10 @@ static void bxt_sanitize_cdclk(struct intel_display
> *display)
> * dividers both syncing to an active pipe, or asynchronously
> * (PIPE_NONE).
> */
> - cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> - cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> + if (DISPLAY_VER(display) < 30) {
> + cdctl &= ~bxt_cdclk_cd2x_pipe_mask(display);
> + cdctl |= bxt_cdclk_cd2x_pipe(display, INVALID_PIPE);
> + }
>
> if (cdctl != expected) {
> if (DISPLAY_VER(display) < 20) {
> --
> 2.54.0
--
Ville Syrjälä
Intel
