On 7/21/2026 8:12 PM, Borah, Chaitanya Kumar wrote:
On 7/20/2026 1:48 PM, Ankit Nautiyal wrote:
From PTL onwards the DSB waits on the VRR safe window instead of vblank
(chicken bit 14 selects the safe window signal from the DPT unit to
bit [15:14]
Thats right.
It is not entirely true that Safe window signal was used only from PTL
onwards. Pre-PTL it was still used but just for VRR.
Yes right I missed to add that we are waiting for safe signal for Fixed
RR case. I will reframe this.
Thanks for pointing these out, will fix these in v2.
Regards,
Ankit
start the DMA engine). The safe window starts at (undelayed vblank
start - set context latency) and ends at the delayed vblank start.
With modes that have a smaller vblank region, the computed guardband is
clamped to the vblank length, which makes the undelayed and delayed
vblank coincide. If the set context latency (SCL) is also 0, the safe
window collapses to 0. The DSB, configured to wait for the safe window,
then stalls forever since the hardware never signals it, leading to:
*ERROR* [CRTC:159:pipe A] flip_done timed out
*ERROR* [CRTC:159:pipe A] DSB 0 timed out waiting for idle
Clamp the set context latency to a minimum of 1 from PTL onwards so the
safe window always keeps a non-zero width.
I could not thoroughly check if there are any side effects of this on
the optimized guardband (and therefore on PSR, LOBF etc.) but the
change looks safe enough to me.
Reviewed-by: Chaitanya Kumar Borah <[email protected]>
Fixes: 4a68c7516c57 ("drm/i915/dsb: Use safe window path when VRR TG
is used")
Cc: Ville Syrjälä <[email protected]>
Signed-off-by: Ankit Nautiyal <[email protected]>
Assisted-by: GitHub-Copilot:Claude-Opus-4.8
---
drivers/gpu/drm/i915/display/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c
b/drivers/gpu/drm/i915/display/intel_display.c
index 38763a6802c5..0822a2194c7f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2459,6 +2459,19 @@ static int
intel_crtc_set_context_latency(struct intel_crtc_state *crtc_state)
set_context_latency = max(set_context_latency,
intel_psr_min_set_context_latency(crtc_state));
+ /*
+ * From PTL onwards, the set context latency can be in the vactive
+ * region, letting the safe window start some lines before the
vblank
+ * start. With modes that have a smaller vblank region, the
computed
+ * guardband is clamped to the vblank length, making the
undelayed and
+ * delayed vblank coincide. If the SCL is also 0, the 'safe window'
+ * becomes effectively 0, and the DSB configured to wait for it
gets
+ * stalled, since the hardware never signals the safe window.
Keep the
+ * set context latency at a minimum of 1 to avoid this.
+ */
+ if (DISPLAY_VER(display) >= 30)
+ set_context_latency = max(1, set_context_latency);
+
return set_context_latency;
}
