On 7/28/2026 8:29 PM, Mitul Golani wrote:
Split the CMRR M/N register programming into intel_vrr_enable_cmrr()
and intel_vrr_disable_cmrr(), and drive them from
intel_vrr_set_fixed_rr_timings() based on crtc_state->vrr.cmrr.enable.
stale commit messageg
VRR_CTL_CMRR_ENABLE is not set explicitly, writing TRANS_CMRR_N_HI
arms CMRR in hardware. Drop the now-unused cmrr_enable
argument to intel_vrr_tg_enable().
No functional change intended for non-CMRR configurations.
--v2:
- Commit message changes.
- Added Simplified enable/disable sequence. (Chaitanya)
--v3:
- Guard CMRR enable condition (Chaitanya)
- Comment changes updated (Chaitanya)
- Squash register write commits together and
avoid double writing issue. (Chaitanya)
--v4:
- Guard CMRR enable/disable with platform check
--v5:
- Update CMRR in enable/disable path
--v6:
- Simplify enable/disable calls (Chaitanya)
- Make function usable for common cmtg and cpu transcoder
(Chaitanya)
Signed-off-by: Mitul Golani <[email protected]>
Assisted-by: Claude:claude-opus-4-8
---
drivers/gpu/drm/i915/display/intel_vrr.c | 59 ++++++++++++++++--------
1 file changed, 40 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c
b/drivers/gpu/drm/i915/display/intel_vrr.c
index 056d513ab637..8d871aa58cab 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -352,6 +352,36 @@ int intel_vrr_fixed_rr_hw_flipline(const struct
intel_crtc_state *crtc_state)
return intel_vrr_fixed_rr_hw_vtotal(crtc_state);
}
+static void
+intel_vrr_set_cmrr_timings(const struct intel_crtc_state *crtc_state,
+ enum transcoder transcoder)
+{
+ struct intel_display *display = to_intel_display(crtc_state);
+
+ if (!intel_vrr_cmrr_possible(crtc_state))
+ return;
+
+ intel_de_write(display, TRANS_CMRR_M_HI(display, transcoder),
+ upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+ intel_de_write(display, TRANS_CMRR_M_LO(display, transcoder),
+ lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
+ intel_de_write(display, TRANS_CMRR_N_LO(display, transcoder),
+ lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+ intel_de_write(display, TRANS_CMRR_N_HI(display, transcoder),
+ upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
+
+ /*
+ * On always-VRR-TG platforms the fastset path does not rewrite the
+ * whole TRANS_VRR_CTL, so RMW only the CMRR enable bit here. On a
+ * modeset the authoritative writes (intel_vrr_tg_enable(),
+ * intel_cmtg_set_vrr_ctl()) carry the same bit, so this stays
+ * consistent.
+ */
+ intel_de_rmw(display, TRANS_VRR_CTL(display, transcoder),
+ VRR_CTL_CMRR_ENABLE,
+ crtc_state->vrr.cmrr.enable ? VRR_CTL_CMRR_ENABLE : 0);
+}
+
void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state,
enum transcoder transcoder)
{
@@ -360,6 +390,8 @@ void intel_vrr_set_fixed_rr_timings(const struct
intel_crtc_state *crtc_state,
if (!intel_vrr_possible(crtc_state))
return;
+ intel_vrr_set_cmrr_timings(crtc_state, transcoder);
+
intel_de_write(display, TRANS_VRR_VMIN(display, transcoder),
intel_vrr_fixed_rr_hw_vmin(crtc_state) - 1);
intel_de_write(display, TRANS_VRR_VMAX(display, transcoder),
@@ -671,17 +703,6 @@ void intel_vrr_set_transcoder_timings(const struct
intel_crtc_state *crtc_state)
return;
}
- if (crtc_state->vrr.cmrr.enable) {
- intel_de_write(display, TRANS_CMRR_M_HI(display,
cpu_transcoder),
- upper_32_bits(crtc_state->vrr.cmrr.cmrr_m));
- intel_de_write(display, TRANS_CMRR_M_LO(display,
cpu_transcoder),
- lower_32_bits(crtc_state->vrr.cmrr.cmrr_m));
- intel_de_write(display, TRANS_CMRR_N_HI(display,
cpu_transcoder),
- upper_32_bits(crtc_state->vrr.cmrr.cmrr_n));
- intel_de_write(display, TRANS_CMRR_N_LO(display,
cpu_transcoder),
- lower_32_bits(crtc_state->vrr.cmrr.cmrr_n));
- }
-
intel_vrr_set_fixed_rr_timings(crtc_state, cpu_transcoder);
intel_cmtg_set_vrr_timings(crtc_state);
@@ -947,8 +968,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state)
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder),
vrr_ctl);
}
-static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state,
- bool cmrr_enable)
+static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state)
{
struct intel_display *display = to_intel_display(crtc_state);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
@@ -960,11 +980,12 @@ static void intel_vrr_tg_enable(const struct
intel_crtc_state *crtc_state,
vrr_ctl = VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state);
/*
- * FIXME this might be broken as bspec seems to imply that
- * even VRR_CTL_CMRR_ENABLE is armed by TRANS_CMRR_N_HI
- * when enabling CMRR (but not when disabling CMRR?).
Please add the reasoning for removal of this comment in the commit
message. The comment below is not a direct replacement. I think the
experiments show that writing VRR_CTL_CMRR_ENABLE after TRANS_CMRR_N_HI
works so the comment is not valid anymore.
Other than that, LGTM
Reviewed-by: Chaitanya Kumar Borah <[email protected]>
+ * This full TRANS_VRR_CTL write is the authoritative one, so it must
+ * carry VRR_CTL_CMRR_ENABLE when CMRR is in use. Writing
TRANS_CMRR_N_HI
+ * arms the bit in hardware, but this later write would otherwise clear
+ * it again.
*/
- if (cmrr_enable)
+ if (crtc_state->vrr.cmrr.enable)
vrr_ctl |= VRR_CTL_CMRR_ENABLE;
intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl);
@@ -1000,7 +1021,7 @@ void intel_vrr_enable(const struct intel_crtc_state
*crtc_state)
intel_vrr_enable_dc_balancing(crtc_state);
if (!intel_vrr_always_use_vrr_tg(display))
- intel_vrr_tg_enable(crtc_state, crtc_state->vrr.cmrr.enable);
+ intel_vrr_tg_enable(crtc_state);
}
void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state)
@@ -1027,7 +1048,7 @@ void intel_vrr_transcoder_enable(const struct
intel_crtc_state *crtc_state)
return;
if (intel_vrr_always_use_vrr_tg(display))
- intel_vrr_tg_enable(crtc_state, false);
+ intel_vrr_tg_enable(crtc_state);
}
void intel_vrr_transcoder_disable(const struct intel_crtc_state *old_crtc_state)
