> -----Original Message-----
> From: Borah, Chaitanya Kumar <[email protected]>
> Sent: Tuesday, September 1, 2026 5:33 PM
> To: [email protected]; [email protected]
> Cc: Shankar, Uma <[email protected]>; Borah, Chaitanya Kumar
> <[email protected]>
> Subject: [v2 2/2] drm/i915/color: Add YUV buffer support on HDR planes
> 
> Add the INTEL_PLANE_CB_CSC_FF (fixed function CSC) color block as the first
> stage for the HDR planes. This enables YUV-to-RGB color space conversion on
> HDR planes via the color pipeline.
> 
> Also in icl_program_input_csc(), account for the color pipeline programming, 
> in
> addition to FB format.
> 
> v2:
>  - Increase MAX_COLOROP to 5 (Sashiko)

Looks Good to me.
Reviewed-by: Uma Shankar <[email protected]>

> Signed-off-by: Chaitanya Kumar Borah <[email protected]>
> ---
>  drivers/gpu/drm/i915/display/intel_color_pipeline.c | 4 +++-
> drivers/gpu/drm/i915/display/skl_universal_plane.c  | 3 ++-
>  2 files changed, 5 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> index 38cfd6ed585d..7fc31fe891a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> +++ b/drivers/gpu/drm/i915/display/intel_color_pipeline.c
> @@ -12,7 +12,7 @@
>  #include "skl_universal_plane.h"
> 
>  #define MAX_COLOR_PIPELINES 1
> -#define MAX_COLOROP 4
> +#define MAX_COLOROP 5
>  #define PLANE_DEGAMMA_SIZE 128
>  #define PLANE_GAMMA_SIZE 32
> 
> @@ -31,6 +31,7 @@ static const struct drm_colorop_funcs intel_colorop_funcs =
> {
>   * the pipeline totally unusable.
>   */
>  static const enum intel_color_block xe3plpd_primary_plane_pipeline[] = {
> +     INTEL_PLANE_CB_CSC_FF,
>       INTEL_PLANE_CB_PRE_CSC_LUT,
>       INTEL_PLANE_CB_CSC,
>       INTEL_PLANE_CB_3DLUT,
> @@ -38,6 +39,7 @@ static const enum intel_color_block
> xe3plpd_primary_plane_pipeline[] = {  };
> 
>  static const enum intel_color_block hdr_plane_pipeline[] = {
> +     INTEL_PLANE_CB_CSC_FF,
>       INTEL_PLANE_CB_PRE_CSC_LUT,
>       INTEL_PLANE_CB_CSC,
>       INTEL_PLANE_CB_POST_CSC_LUT,
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index 0f604bdb4c62..2e5bf02b480f 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -1626,7 +1626,8 @@ icl_plane_update_noarm(struct intel_dsb *dsb,
>       intel_de_write_dsb(display, dsb, PLANE_COLOR_CTL(pipe, plane_id),
>                          plane_color_ctl);
> 
> -     if (fb->format->is_yuv && icl_is_hdr_plane(display, plane_id))
> +     if (icl_is_hdr_plane(display, plane_id) &&
> +         (fb->format->is_yuv || plane_state->hw.csc_ff_enable))
>               icl_program_input_csc(dsb, plane, plane_state);
> 
>       skl_write_plane_wm(dsb, plane, crtc_state);
> --
> 2.50.1

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