> -----Original Message----- > From: Jani Nikula <[email protected]> > Sent: Wednesday, 2 September 2026 15.00 > To: Kahola, Mika <[email protected]>; [email protected]; > [email protected] > Cc: [email protected]; Kahola, Mika <[email protected]> > Subject: Re: [PATCH v2 1/2] drm/i915/display: Reject flipq for pipe or timing > changes > > On Wed, 02 Sep 2026, Mika Kahola <[email protected]> wrote: > > Our flipq eligibility check let pipe, M/N and LRR changes through. > > Reject those too, alongside the existing async flip/VRR/PSR/color/ > > modeset/fastset exclusions. > > Why?
Sashiko spotted that this part we cannot reach /* + * Flipq is only suitable for simple queued plane updates that do + * not require additional pipe or timing programming. + */ + if (new_crtc_state->update_pipe || + new_crtc_state->update_m_n || + new_crtc_state->update_lrr) + return false; update_pipe is already checked via intel_crtc_needs_fastset() and if update_pipe is true also the update_lrr and update_m_n are true as well. So the whole patch reduced to one liner checking only the update_planes https://patchwork.freedesktop.org/patch/750148/?series=171792&rev=3 > > > > > v2: > > - Drop the single-plane restriction, plane count doesn't matter (Ville) > > - Drop the update_wm_pre/post check, dead code for flipq-capable hw (Ville) > > - Drop the active/enabled planes check (Ville) > > > > Assisted-by: Copilot:claude-sonnet-5 > > Signed-off-by: Mika Kahola <[email protected]> > > --- > > drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++---- > > 1 file changed, 36 insertions(+), 7 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c > > b/drivers/gpu/drm/i915/display/intel_display.c > > index 553c60d452dd..f4b76a9547e3 100644 > > --- a/drivers/gpu/drm/i915/display/intel_display.c > > +++ b/drivers/gpu/drm/i915/display/intel_display.c > > @@ -7369,6 +7369,41 @@ static void > > intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s > > } > > } > > > > +static bool intel_flipq_commit_is_eligible(struct intel_atomic_state > > *state, > > + struct intel_crtc *crtc) > > +{ > > + struct intel_display *display = to_intel_display(state); > > + const struct intel_crtc_state *new_crtc_state = > > + intel_atomic_get_new_crtc_state(state, crtc); > > + > > + if (!intel_flipq_supported(display)) > > + return false; > > + > > + if (intel_crtc_needs_modeset(new_crtc_state) || > > + intel_crtc_needs_fastset(new_crtc_state) || > > + intel_crtc_needs_color_update(new_crtc_state)) > > + return false; > > + > > + if (!new_crtc_state->update_planes) > > + return false; > > + > > + if (new_crtc_state->do_async_flip || > > + new_crtc_state->vrr.enable || > > + new_crtc_state->has_psr) > > + return false; > > + > > + /* > > + * Flipq is only suitable for simple queued plane updates that do > > + * not require additional pipe or timing programming. > > + */ > > + if (new_crtc_state->update_pipe || > > + new_crtc_state->update_m_n || > > + new_crtc_state->update_lrr) > > + return false; > > + > > + return true; > > +} > > + > > static void intel_atomic_dsb_prepare(struct intel_atomic_state *state, > > struct intel_crtc *crtc) > > { > > @@ -7384,13 +7419,7 @@ static void intel_atomic_dsb_prepare(struct > > intel_atomic_state *state, > > > > /* FIXME deal with everything */ > > new_crtc_state->use_flipq = > > - intel_flipq_supported(display) && > > - !new_crtc_state->do_async_flip && > > - !new_crtc_state->vrr.enable && > > - !new_crtc_state->has_psr && > > - !intel_crtc_needs_modeset(new_crtc_state) && > > - !intel_crtc_needs_fastset(new_crtc_state) && > > - !intel_crtc_needs_color_update(new_crtc_state); > > + intel_flipq_commit_is_eligible(state, crtc); > > > > new_crtc_state->use_dsb = > > !new_crtc_state->use_flipq && > > -- > Jani Nikula, Intel
