On Wed, 2026-09-03 Jouni Högander wrote: > Thank you for the patch. Have you tried increasing vblank/guardband > alone? > ... > Have you tried fiddling with the fast wake sync pulse count? See > driver/gpu/drm/i915/display/intel_dp_auc.c:intel_dp_aux_fw_sync_len.
Tried both today. Each run is 15 s of PSR2 with DP_PSR_ERROR_STATUS polled every 200 ms and cleared after every read, so the number is how many polls found the Link CRC error bit set again: io/fast 11/11, guardband 60 (stock) 70 of 71 io/fast 11/11, guardband 127 (full vblank) 70 of 70 fw sync len 20 -> io/fast 12/12 68 of 69 fw sync len 24 -> io/fast 13/13 69 of 70 io/fast 11/12 (this patch) 0 of 71 Guardband and sync pulse length make no difference, and moving both wake times up together doesn't either. Only fast > io does. > Your change is conflicting with the spec. It might be a trace to the > actual problem. Understood. I'll respin it as a quirk for this panel (LG, sink OUI 00:22:b9, the DA14260/DA16260 pair) unless you prefer a different key. DPCD OUI quirk or the device id table next to the Panel Replay entry, whichever you want. For what it's worth, with the stock 11/11 the screen keeps updating under PSR2 only because every wake fails and the sink resyncs (0x2008 reads 3 the whole time). With the wake clean, the SU problem from the other thread is what you get. Jake
