The driver currently computes the Adaptive Sync SDP transmission line directly at programming time. Instead, compute and store the AS SDP transmission line in the crtc state and use it when programming the EMP_AS_SDP_TL register.
We get the clear picture about the SDPs and guardband only in intel_dp_sdp_compute_config_late() therefore we must configure the AS SDP transmission line at this point when AS SDP is enabled in crtc_state. This prepares the ground for supporting programmable transmission lines for additional DP SDPs. While moving the helper into intel_dip.c, drop the intel_crtc_has_dp_encoder() check instead of relocating it. It was needed in the old VRR write path shared by other encoderes as well, but intel_dip_sdp_tl_compute_config_late() is only reached via DP, so HDMI never sets crtc_state->dip.emp_as_sdp_tl and it stays 0 by default. v2: - Move the helper into intel_dip.c and drop the intel_crtc_has_dp_encoder() check. - Drop the redundant checks. (Suraj) Signed-off-by: Ankit Nautiyal <[email protected]> --- drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++ drivers/gpu/drm/i915/display/intel_dip.c | 20 +++++++++++--------- drivers/gpu/drm/i915/display/intel_dip.h | 3 +++ drivers/gpu/drm/i915/display/intel_dp.c | 2 ++ 4 files changed, 18 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c index 9b3b526e5e55..dacb4b7588a0 100644 --- a/drivers/gpu/drm/i915/display/intel_ddi.c +++ b/drivers/gpu/drm/i915/display/intel_ddi.c @@ -49,6 +49,7 @@ #include "intel_ddi.h" #include "intel_ddi_buf_trans.h" #include "intel_de.h" +#include "intel_dip.h" #include "intel_display_power.h" #include "intel_display_regs.h" #include "intel_display_types.h" @@ -4235,6 +4236,7 @@ static void intel_ddi_get_config(struct intel_encoder *encoder, intel_read_dp_sdp(encoder, pipe_config, HDMI_PACKET_TYPE_GAMUT_METADATA); intel_read_dp_sdp(encoder, pipe_config, DP_SDP_VSC); intel_read_dp_sdp(encoder, pipe_config, DP_SDP_ADAPTIVE_SYNC); + intel_dip_sdp_transmission_line_get_config(pipe_config); intel_audio_codec_get_config(encoder, pipe_config); } diff --git a/drivers/gpu/drm/i915/display/intel_dip.c b/drivers/gpu/drm/i915/display/intel_dip.c index 0277b15e1c82..d1acc7eb5a39 100644 --- a/drivers/gpu/drm/i915/display/intel_dip.c +++ b/drivers/gpu/drm/i915/display/intel_dip.c @@ -43,19 +43,21 @@ void intel_dip_write_emp_as_sdp_tl(const struct intel_crtc_state *crtc_state) { struct intel_display *display = to_intel_display(crtc_state); enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; - u32 transmission_line = 0; if (!HAS_EMP_AS_SDP_TL(display)) return; - /* - * Since we currently support VRR only for DP/eDP, program the register - * for Adaptive Sync SDP using vsync start. For non-DP encoders, - * the register is reset to 0. - */ - if (intel_crtc_has_dp_encoder(crtc_state)) - transmission_line = intel_dip_get_as_sdp_transmission_line(crtc_state); intel_de_write(display, EMP_AS_SDP_TL(display, cpu_transcoder), - EMP_AS_SDP_DB_TL(transmission_line)); + EMP_AS_SDP_DB_TL(crtc_state->dip.emp_as_sdp_tl)); +} + +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state) +{ + crtc_state->dip.emp_as_sdp_tl = intel_dip_get_as_sdp_transmission_line(crtc_state); +} + +void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state) +{ + crtc_state->dip.emp_as_sdp_tl = intel_dip_read_emp_as_sdp_tl(crtc_state); } diff --git a/drivers/gpu/drm/i915/display/intel_dip.h b/drivers/gpu/drm/i915/display/intel_dip.h index 37507ac3e645..600dabbf7372 100644 --- a/drivers/gpu/drm/i915/display/intel_dip.h +++ b/drivers/gpu/drm/i915/display/intel_dip.h @@ -43,4 +43,7 @@ struct intel_dip { u16 emp_as_sdp_tl; }; +void intel_dip_sdp_tl_compute_config_late(struct intel_crtc_state *crtc_state); +void intel_dip_sdp_transmission_line_get_config(struct intel_crtc_state *crtc_state); + #endif /* __INTEL_DIP_H__ */ diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 0cd5e6b5034c..eed4fca2b985 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -7324,6 +7324,8 @@ int intel_dp_sdp_compute_config_late(struct intel_crtc_state *crtc_state) return -EINVAL; } + intel_dip_sdp_tl_compute_config_late(crtc_state); + return 0; } -- 2.50.1
