Its observed that on AUX_CH failure, even if the retry is increased to
1000, it does not succeed. Either the command might be wrong or sink in
an unknown/sleep state can cause this. So try waking the sink device.
Before reading the DPCD caps wake the sink for eDP.
v2: Use poll_timeout_us (Jani N)
Add the reason, why this change is required (Ville)
v3: Wake sink only for eDP
Remove the dpcd probe set to true/false in wake_sink (Imre)
v4: make edp_wake_sinc() static and dpcd_readb -> dpcd_reab_byte (Suraj)
v5: Drop poll_timeout_us. drm_dp_dpcd_read_byte() already retries the AUX
transaction internally (up to ~16ms), so the outer 6ms poll could
never iterate and only added a pre-read delay on the hot path; read
DP_SET_POWER once instead. Wake the sink before reading the DPCD
caps, otherwise a sleeping sink fails the caps read and returns
early before the wake ever runs. (Suraj, Jani, Sashiko)
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/4391
Closes: https://gitlab.freedesktop.org/drm/i915/kernel/-/work_items/16654
Signed-off-by: Arun R Murthy <[email protected]>
---
drivers/gpu/drm/i915/display/intel_dp.c | 33 +++++++++++++++++++++++++
1 file changed, 33 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
b/drivers/gpu/drm/i915/display/intel_dp.c
index 0cd5e6b5034c..07cc39a6f2e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4779,6 +4779,33 @@ intel_edp_set_sink_rates(struct intel_dp *intel_dp)
intel_edp_set_data_override_rates(intel_dp);
}
+static void intel_edp_wake_sink(struct intel_dp *intel_dp)
+{
+ u8 value = 0;
+ int ret;
+
+ /*
+ * Read the current sink power state. drm_dp_dpcd_read_byte() already
+ * retries the AUX transaction internally, so a single read suffices.
+ * First commercial eDP panels are Ver1.0 or 1.1, on which DPCD
+ * DP_SET_POWER is supported.
+ */
+ ret = drm_dp_dpcd_read_byte(&intel_dp->aux, DP_SET_POWER, &value);
+
+ /*
+ * If the AUX read failed the sink may be asleep and not responding,
+ * or it read back D3; in either case wake it up to D3_AUX_ON.
+ */
+ if (ret < 0 || value == DP_SET_POWER_D3) {
+ /* After setting to D0 need a min of 1ms to wake (Spec DP2.1
sec 2.3.1.2) */
+ drm_dp_dpcd_write_byte(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D0);
+ fsleep(1000);
+ drm_dp_dpcd_write_byte(&intel_dp->aux, DP_SET_POWER,
+ DP_SET_POWER_D0);
+ }
+}
+
static bool
intel_edp_init_dpcd(struct intel_dp *intel_dp, struct intel_connector
*connector)
{
@@ -4789,6 +4816,12 @@ intel_edp_init_dpcd(struct intel_dp *intel_dp, struct
intel_connector *connector
/* this function is meant to be called only once */
drm_WARN_ON(display->drm, intel_dp->dpcd[DP_DPCD_REV] != 0);
+ /*
+ * Spec DP2.1 Section 3.5.2.16 page 966.
+ * Also if sink is asleep, this will wake the sink.
+ */
+ intel_edp_wake_sink(intel_dp);
+
if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0)
return false;
--
2.25.1
