Update, details and files on the gitlab issue: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/9119
Jouni posted an xe_reg_rw trace from a PTL system where Panel Replay works (1920x1200 panel, no DSC). I captured the same trace here and diffed the two. The PR enable sequence and every PSR, ALPM, VRR and push register match, apart from fields derived from the panel timing and link rate. What is left: this panel needs DSC (2 VDSC engines, 10 bpc input), his does not; DC6 is allowed on his system and blocked here by the compositor keeping vblank enabled; PSR_IMR. Second finding: in Panel Replay, which uses the aux-less ALPM wake here, the sink latches the Link CRC error in DP_PANEL_REPLAY_ERROR_STATUS on every compositor commit (about 40 of 86 polls over 20 s, tracking a blinking cursor). It does not depend on the aux-less wake lines, the PORT_ALPM_CTL silence period, the LFPS half cycle or cycle count, PHY swing hold, sleep hold, or the sink's CRC verification bits. PSR1 polled the same way stays clean. So PR here is the same failed-wake resync loop PSR2 had before the fast wake patch, and PSR2 with that patch is the other half: clean link, no SU_VALID ever, engine parked in SU_STANDBY, frozen panel. One driver observation: enabling PR through the i915_edp_psr_debug fastset does not program PORT_ALPM_CTL / PORT_ALPM_LFPS_CTL, since intel_alpm_port_configure() only runs from the DDI enable path. Open question: is there a PTL system with a DSC eDP panel where PR or PSR2 selective update is confirmed working? The other two PTL reports (#8924, #8930) are 2880x1800 and 2560x1600 at 120 Hz panels. Jake
