When Panel Replay is active the transcoder timing generator runs at the
panel's maximum refresh rate, but content is often presented at a lower
rate. In that case the Adaptive-Sync SDP (AS SDP) only needs to reach the
panel often enough to satisfy its maximum frame time, so transmitting it
on every frame is redundant and shows up as repeated SDPs on the link.
Xe3LPD adds a HW skip-frame counter in PR_ALPM_CTL that lets the source
send a single AS SDP and then suppress it for a programmed number of
frames. Program this counter so that one AS SDP is followed by
(max_vrefresh / flip_rate - 1) idle frames, matching the effective
content rate and allowing the link to be driven down to as low as 1Hz
when the hardware supports it.
v5: Drop module param and add debugfs
v4:
- Fix Sashiko review comments
v3:
- Add module parameter
- Fix Skip count clearing issue (Dibin)
- Add DC3Co checks and enabling conditions
Uma Shankar (4):
drm/i915/display: Enable periodic AS SDP skip frames
drm/i915/display: Force disable DC3co when AS SDP skip frames is
enabled
drm/i915/display: Reprogram AS SDP skip frames on seamless VRR
transitions
drm/i915/display: Gate periodic AS SDP skip frames behind a debugfs
knob
drivers/gpu/drm/i915/display/intel_alpm.c | 154 ++++++++++++++++--
drivers/gpu/drm/i915/display/intel_alpm.h | 3 +
drivers/gpu/drm/i915/display/intel_display.c | 18 ++
.../drm/i915/display/intel_display_params.h | 5 +
.../drm/i915/display/intel_display_power.c | 9 +
drivers/gpu/drm/i915/display/intel_psr_regs.h | 2 +
6 files changed, 175 insertions(+), 16 deletions(-)
--
2.50.1
