Selective fetch is dropped while pipe CRC is active, but the per-plane
SEL_FETCH_PLANE_CTL()/SEL_FETCH_CUR_CTL() enable bits stay set in
hardware. A plane disabled during that window never gets its bit cleared,
since the disable path is guarded by enable_psr2_sel_fetch. When selective
fetch returns, hardware keeps fetching for a plane that is gone and holds
its DDB range.
Commit 7f1172a2ac0d ("drm/i915/display: Clear SEL_FETCH_PLANE_CTL on
plane disable") fixed that by swapping the guard for
HAS_PSR2_SEL_FETCH(), but that caused unclaimed register access on
pipes driving HDMI.
Patch 1 reverts it. Patch 2 clears the bits at the point selective fetch
is turned off instead. Atomic check has both the old and the new crtc
state, so record the transition there and let the plane and cursor arm
paths write the registers to 0 for that commit.
Nemesa Garg (2):
Revert "drm/i915/display: Clear SEL_FETCH_PLANE_CTL on plane disable"
drm/i915/psr: Clear stale sel fetch enable bits on sel fetch disable
drivers/gpu/drm/i915/display/intel_cursor.c | 20 ++++++++---------
.../drm/i915/display/intel_display_types.h | 6 +++++
drivers/gpu/drm/i915/display/intel_psr.c | 19 ++++++++++++++++
.../drm/i915/display/skl_universal_plane.c | 22 +++++++------------
4 files changed, 42 insertions(+), 25 deletions(-)
--
2.25.1
