On 9/9/2026 9:47 PM, Ville Syrjala wrote:
From: Ville Syrjälä <[email protected]> Use intel_color_uses_chained_dsb() rather than intel_color_uses_dsb() when deciding whether to evade the undelayed vblank/SCL in the mmio based commit path. A non-chained DSB will not wait for the undelayed vblank/safe window before starting execution, and the LUT itself will be double buffered in this case. Thus we only need to evade the delayed vblank.
LGTM Reviewed-by: Chaitanya Kumar Borah <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]> --- drivers/gpu/drm/i915/display/intel_vblank.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vblank.c b/drivers/gpu/drm/i915/display/intel_vblank.c index 28d81199792e..72e04c4f0303 100644 --- a/drivers/gpu/drm/i915/display/intel_vblank.c +++ b/drivers/gpu/drm/i915/display/intel_vblank.c @@ -724,10 +724,10 @@ void intel_vblank_evade_init(const struct intel_crtc_state *old_crtc_state, * undelayed vblank, so with seamless M/N and LRR we must evade * both vblanks. * - * DSB execution waits for the transcoder's undelayed vblank, - * hence we must kick off the commit before that. + * Chained DSB execution waits for the transcoder's undelayed + * vblank, hence we must kick off the commit before that. */ - if (intel_color_uses_dsb(new_crtc_state) || + if (intel_color_uses_chained_dsb(new_crtc_state) || new_crtc_state->update_m_n || new_crtc_state->update_lrr) evade->min -= vblank_delay; }
