I think the patch order may need to be adjusted: swap this patch with patch 2 and move the current patch 2 to position 3.
> -----Original Message----- > From: Kandpal, Suraj <[email protected]> > Sent: 21 October 2026 12:44 > To: [email protected]; [email protected] > Cc: Golani, Mitulkumar Ajitkumar <[email protected]>; > Kandpal, Suraj <[email protected]> > Subject: [PATCH v6 03/11] drm/i915/display_wa: Add support for > Wa_14014191401 > > The DG2 transcoder timing generator DDA only supports a Link M/N ratio of > up to 4. The Link M/N ratio limit uses a bare platform check for it. > > Add Wa_14014191401 for DG2 and use it for the limit instead. > > Signed-off-by: Suraj Kandpal <[email protected]> > --- > drivers/gpu/drm/i915/display/intel_display_wa.c | 2 ++ > drivers/gpu/drm/i915/display/intel_display_wa.h | 1 + > drivers/gpu/drm/i915/display/intel_dp.c | 3 ++- > 3 files changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c > b/drivers/gpu/drm/i915/display/intel_display_wa.c > index 2e3ff4861ef4..91395076e903 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_wa.c > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.c > @@ -94,6 +94,8 @@ bool __intel_display_wa(struct intel_display *display, > enum intel_display_wa wa, > IS_DISPLAY_STEP(display, STEP_A0, STEP_A2); > case INTEL_DISPLAY_WA_14014143976: > return IS_DISPLAY_STEP(display, STEP_E0, STEP_FOREVER); > + case INTEL_DISPLAY_WA_14014191401: > + return display->platform.dg2; > case INTEL_DISPLAY_WA_14016740474: > return IS_DISPLAY_VERx100_STEP(display, 1400, STEP_A0, > STEP_C0); > case INTEL_DISPLAY_WA_14020863754: > diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h > b/drivers/gpu/drm/i915/display/intel_display_wa.h > index b707147a7587..f41e58d1d6e7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_wa.h > +++ b/drivers/gpu/drm/i915/display/intel_display_wa.h > @@ -31,6 +31,7 @@ enum intel_display_wa { > INTEL_DISPLAY_WA_14011508470, > INTEL_DISPLAY_WA_14011765242, > INTEL_DISPLAY_WA_14014143976, > + INTEL_DISPLAY_WA_14014191401, > INTEL_DISPLAY_WA_14016740474, > INTEL_DISPLAY_WA_14020863754, > INTEL_DISPLAY_WA_14025769978, > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index 7ceb7c02b597..f3a79ae49b18 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -70,6 +70,7 @@ > #include "intel_display_regs.h" > #include "intel_display_rpm.h" > #include "intel_display_types.h" > +#include "intel_display_wa.h" > #include "intel_dp.h" > #include "intel_dp_aux.h" > #include "intel_dp_hdcp.h" > @@ -1271,7 +1272,7 @@ bool intel_dp_has_dsc(const struct intel_connector > *connector) static int intel_dp_get_max_m_n_ratio(struct intel_display > *display) { > - if (display->platform.dg2) > + if (intel_display_wa(display, INTEL_DISPLAY_WA_14014191401)) With above suggested change is done, LGTM Reviewed-by: Mitul Golani<[email protected]> > return 4; > > return 10; > -- > 2.34.1
