Thank you for your contribution! Sashiko AI review found 1 potential issue to consider: - [Medium] drm/i915/dp: intel_dp_joiner_valid_primary_pipe_mask() allows 4-pipe eDP joiner --
commit fe84695283ce600e9fd16b2acfa62f5dd071d260 Author: Mika Kahola <[email protected]> drm/i915/display: Limit the eDP joiner to the pipe A and B pair This commit adds intel_dp_joiner_valid_primary_pipe_mask() to restrict joined eDP configurations to primary pipe A during mode validation and link configuration. > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c > b/drivers/gpu/drm/i915/display/intel_dp.c > index ef164a7976187..b359a66a018f4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -1362,16 +1362,27 @@ static int intel_dp_mso_pixel_clock(struct intel_dp > *intel_dp, int pixel_clock) > return pixel_clock / intel_dp->mso_link_count; > } > > +/* eDP can only be joined as the pipe A and B pair. */ > +static u8 intel_dp_joiner_valid_primary_pipe_mask(struct intel_dp *intel_dp, > + int num_joined_pipes) > +{ > + struct intel_display *display = to_intel_display(intel_dp); > + u8 pipe_mask = intel_joiner_valid_primary_pipe_mask(display, > num_joined_pipes); > + > + if (num_joined_pipes > 1 && intel_dp_is_edp(intel_dp)) > + pipe_mask &= BIT(PIPE_A); > + > + return pipe_mask; > +} [Severity: Medium] Does intel_dp_joiner_valid_primary_pipe_mask() still allow 4-pipe ultrajoiner (pipes A, B, C, and D) on eDP when num_joined_pipes == 4? On platforms with HAS_ULTRAJOINER(display), intel_joiner_valid_primary_pipe_mask(display, 4) returns BIT(PIPE_A) because pipe A is the primary pipe for joining 4 consecutive pipes. Masking pipe_mask with BIT(PIPE_A) when num_joined_pipes > 1 leaves BIT(PIPE_A) set for num_joined_pipes == 4 instead of rejecting num_joined_pipes > 2, so intel_dp_can_join() and intel_dp_compute_link_config() on pipe A can still select a 4-pipe joiner configuration (crtc_state->joiner_pipes = GENMASK(3, 0)). Also, on DISPLAY_VER(display) == 11 where intel_dp_has_joiner() allows non-PORT_A encoders and joiner_pipes() in intel_display.c only permits BIT(PIPE_B) | BIT(PIPE_C), masking with BIT(PIPE_A) rejects PIPE_B while leaving PIPE_A to fail later in intel_atomic_check_joiner(). Additionally, i915_joiner_write() in intel_display_debugfs.c still validates force_joined_pipes against intel_joiner_valid_primary_pipe_mask() directly. -- Sashiko AI review · https://sashiko.dev/#/patchset/[email protected]?part=1
