HDC_CHICKEN0 bit 14 (Fence Destination To SLM Disable) must be programmed by software to 1h (Disable) to work around a LSLM unit issue.
WaDisableFenceDestinationToSLM is only needed for BDW E,F step. Signed-off-by: Michel Thierry <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index ce70aa4..b8308cf 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4701,6 +4701,7 @@ enum punit_power_well { /* GEN8 chicken */ #define HDC_CHICKEN0 0x7300 +#define HDC_FENCE_DESTINATION_TO_SLM_DISABLE (1<<14) #define HDC_FORCE_NON_COHERENT (1<<4) /* WaCatErrorRejectionIssue */ diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 6e03851..2c3087f 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5449,9 +5449,11 @@ static void gen8_init_clock_gating(struct drm_device *dev) /* Use Force Non-Coherent whenever executing a 3D context. This is a * workaround for for a possible hang in the unlikely event a TLB * invalidation occurs during a PSD flush. + * WaDisableFenceDestinationToSLM:bdw */ I915_WRITE(HDC_CHICKEN0, I915_READ(HDC_CHICKEN0) | + _MASKED_BIT_ENABLE(HDC_FENCE_DESTINATION_TO_SLM_DISABLE) | _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); /* WaVSRefCountFullforceMissDisable:bdw */ -- 1.9.0 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
