On Tue, 5 Aug 2014 07:51:22 -0700 Rodrigo Vivi <[email protected]> wrote:
> From: Vandana Kannan <[email protected]> > > For Gen < 8, set M2_N2 registers on every mode set. This is required to make > sure M2_N2 registers are set during boot, resume from sleep for cross- > checking the state. The register is set only if DRRS is supported. > > v2: Patch rebased > > v3: Daniel's review comments > - Removed HAS_DRRS(dev) and added bool has_drrs to pipe_config to > track drrs support > > v4: Jesse's review comments > - Made changes to set m2_n2 in intel_dp_set_m_n() > > Signed-off-by: Vandana Kannan <[email protected]> > Cc: Daniel Vetter <[email protected]> > Cc: Jesse Barnes <[email protected]> > Signed-off-by: Rodrigo Vivi <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 28 +++++++++++++++++++++------- > drivers/gpu/drm/i915/intel_dp.c | 18 +++--------------- > drivers/gpu/drm/i915/intel_drv.h | 3 ++- > 3 files changed, 26 insertions(+), 23 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 99eb7ca..e798acd 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -91,11 +91,11 @@ static int intel_framebuffer_init(struct drm_device *dev, > struct intel_framebuffer *ifb, > struct drm_mode_fb_cmd2 *mode_cmd, > struct drm_i915_gem_object *obj); > -static void intel_dp_set_m_n(struct intel_crtc *crtc); > static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc); > static void intel_set_pipe_timings(struct intel_crtc *intel_crtc); > static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > - struct intel_link_m_n *m_n); > + struct intel_link_m_n *m_n, > + struct intel_link_m_n *m2_n2); > static void ironlake_set_pipeconf(struct drm_crtc *crtc); > static void haswell_set_pipeconf(struct drm_crtc *crtc); > static void intel_set_pipe_csc(struct drm_crtc *crtc); > @@ -3980,7 +3980,7 @@ static void ironlake_crtc_enable(struct drm_crtc *crtc) > > if (intel_crtc->config.has_pch_encoder) { > intel_cpu_transcoder_set_m_n(intel_crtc, > - &intel_crtc->config.fdi_m_n); > + &intel_crtc->config.fdi_m_n, NULL); > } > > ironlake_set_pipeconf(crtc); > @@ -4093,7 +4093,7 @@ static void haswell_crtc_enable(struct drm_crtc *crtc) > > if (intel_crtc->config.has_pch_encoder) { > intel_cpu_transcoder_set_m_n(intel_crtc, > - &intel_crtc->config.fdi_m_n); > + &intel_crtc->config.fdi_m_n, NULL); > } > > haswell_set_pipeconf(crtc); > @@ -5509,7 +5509,8 @@ static void intel_pch_transcoder_set_m_n(struct > intel_crtc *crtc, > } > > static void intel_cpu_transcoder_set_m_n(struct intel_crtc *crtc, > - struct intel_link_m_n *m_n) > + struct intel_link_m_n *m_n, > + struct intel_link_m_n *m2_n2) > { > struct drm_device *dev = crtc->base.dev; > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -5521,6 +5522,18 @@ static void intel_cpu_transcoder_set_m_n(struct > intel_crtc *crtc, > I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); > I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); > I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); > + /* M2_N2 registers to be set only for gen < 8 (M2_N2 available > + * for gen < 8) and if DRRS is supported (to make sure the > + * registers are not unnecessarily accessed). > + */ > + if (m2_n2 && INTEL_INFO(dev)->gen < 8 && > + crtc->config.has_drrs) { > + I915_WRITE(PIPE_DATA_M2(transcoder), > + TU_SIZE(m2_n2->tu) | m2_n2->gmch_m); > + I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); > + I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); > + I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); > + } > } else { > I915_WRITE(PIPE_DATA_M_G4X(pipe), TU_SIZE(m_n->tu) | > m_n->gmch_m); > I915_WRITE(PIPE_DATA_N_G4X(pipe), m_n->gmch_n); > @@ -5529,12 +5542,13 @@ static void intel_cpu_transcoder_set_m_n(struct > intel_crtc *crtc, > } > } > > -static void intel_dp_set_m_n(struct intel_crtc *crtc) > +void intel_dp_set_m_n(struct intel_crtc *crtc) > { > if (crtc->config.has_pch_encoder) > intel_pch_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); > else > - intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n); > + intel_cpu_transcoder_set_m_n(crtc, &crtc->config.dp_m_n, > + &crtc->config.dp_m2_n2); > } > > static void vlv_update_pll(struct intel_crtc *crtc) > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index ea6ff71..7290976 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -828,20 +828,6 @@ intel_dp_set_clock(struct intel_encoder *encoder, > } > } > > -static void > -intel_dp_set_m2_n2(struct intel_crtc *crtc, struct intel_link_m_n *m_n) > -{ > - struct drm_device *dev = crtc->base.dev; > - struct drm_i915_private *dev_priv = dev->dev_private; > - enum transcoder transcoder = crtc->config.cpu_transcoder; > - > - I915_WRITE(PIPE_DATA_M2(transcoder), > - TU_SIZE(m_n->tu) | m_n->gmch_m); > - I915_WRITE(PIPE_DATA_N2(transcoder), m_n->gmch_n); > - I915_WRITE(PIPE_LINK_M2(transcoder), m_n->link_m); > - I915_WRITE(PIPE_LINK_N2(transcoder), m_n->link_n); > -} > - > bool > intel_dp_compute_config(struct intel_encoder *encoder, > struct intel_crtc_config *pipe_config) > @@ -867,6 +853,7 @@ intel_dp_compute_config(struct intel_encoder *encoder, > pipe_config->has_pch_encoder = true; > > pipe_config->has_dp_encoder = true; > + pipe_config->has_drrs = false; > pipe_config->has_audio = intel_dp->has_audio; > > if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { > @@ -970,6 +957,7 @@ found: > > if (intel_connector->panel.downclock_mode != NULL && > intel_dp->drrs_state.type == SEAMLESS_DRRS_SUPPORT) { > + pipe_config->has_drrs = true; > intel_link_compute_m_n(bpp, lane_count, > intel_connector->panel.downclock_mode->clock, > pipe_config->port_clock, > @@ -4378,7 +4366,7 @@ void intel_dp_set_drrs_state(struct drm_device *dev, > int refresh_rate) > val = I915_READ(reg); > if (index > DRRS_HIGH_RR) { > val |= PIPECONF_EDP_RR_MODE_SWITCH; > - intel_dp_set_m2_n2(intel_crtc, &config->dp_m2_n2); > + intel_dp_set_m_n(intel_crtc); > } else { > val &= ~PIPECONF_EDP_RR_MODE_SWITCH; > } > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index fada887..1f675a8 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -324,6 +324,7 @@ struct intel_crtc_config { > > /* m2_n2 for eDP downclock */ > struct intel_link_m_n dp_m2_n2; > + bool has_drrs; > > /* > * Frequence the dpll for the port should run at. Differs from the > @@ -876,6 +877,7 @@ void hsw_enable_pc8(struct drm_i915_private *dev_priv); > void hsw_disable_pc8(struct drm_i915_private *dev_priv); > void intel_dp_get_m_n(struct intel_crtc *crtc, > struct intel_crtc_config *pipe_config); > +void intel_dp_set_m_n(struct intel_crtc *crtc); > int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n > *m_n); > void > ironlake_check_encoder_dotclock(const struct intel_crtc_config *pipe_config, > @@ -891,7 +893,6 @@ void intel_mode_from_pipe_config(struct drm_display_mode > *mode, > int intel_format_to_fourcc(int format); > void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc); > > - > /* intel_dp.c */ > void intel_dp_init(struct drm_device *dev, int output_reg, enum port port); > bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, There's an unnecessary gen8 check in there, but this one has my Reviewed-by: Jesse Barnes <[email protected]> -- Jesse Barnes, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
