On Tue, Aug 05, 2014 at 07:51:16AM -0700, Rodrigo Vivi wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> If the object is already UC leave it as UC instead of automagically
> promoting it to WT in i915_gem_object_pin_to_display_plane() when
> the hardware is WT capable.
>
> Supposedly the user wanted UC for a reason, so let's respect that.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.v...@intel.com>
We don't have a use case for this, so can be dropped.
-Daniel
> ---
> drivers/gpu/drm/i915/i915_gem.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index dcd8d7b..5710571 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -3840,6 +3840,7 @@ i915_gem_object_pin_to_display_plane(struct
> drm_i915_gem_object *obj,
> struct intel_engine_cs *pipelined)
> {
> u32 old_read_domains, old_write_domain;
> + unsigned int cache_level;
> bool was_pin_display;
> int ret;
>
> @@ -3864,8 +3865,12 @@ i915_gem_object_pin_to_display_plane(struct
> drm_i915_gem_object *obj,
> * of uncaching, which would allow us to flush all the LLC-cached data
> * with that bit in the PTE to main memory with just one PIPE_CONTROL.
> */
> - ret = i915_gem_object_set_cache_level(obj,
> - HAS_WT(obj->base.dev) ?
> I915_CACHE_WT : I915_CACHE_NONE);
> + if (HAS_WT(obj->base.dev) && obj->cache_level != I915_CACHE_NONE)
> + cache_level = I915_CACHE_WT;
> + else
> + cache_level = I915_CACHE_NONE;
> +
> + ret = i915_gem_object_set_cache_level(obj, cache_level);
> if (ret)
> goto err_unpin_display;
>
> --
> 1.9.3
>
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
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--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
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