On Thu, Aug 07, 2014 at 05:03:30PM +0530, Gajanan Bhat wrote: > Program DDL register as part of sprite watermark programming for CHV and VLV. > > v2: Rename DRAIN_LATENCY_MAX by DRAIN_LATENCY_MASK > > v3: Addressed review comments by Ville > - Changed Sprite DDL definitions to more generic to avoid multiple if-else > - Changed bit masking to customary form > - Changed to bitwise shorthand operator for sprite_dl assignment > > Signed-off-by: Gajanan Bhat <[email protected]>
Looks good. Reviewed-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 9 +++------ > drivers/gpu/drm/i915/intel_pm.c | 33 +++++++++++++++++++++++++++++++++ > 2 files changed, 36 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 08916df..f8aaf0b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -4000,12 +4000,9 @@ enum punit_power_well { > #define DDL_CURSOR_PRECISION_64 (1<<31) > #define DDL_CURSOR_PRECISION_32 (0<<31) > #define DDL_CURSOR_SHIFT 24 > -#define DDL_SPRITE1_PRECISION_64 (1<<23) > -#define DDL_SPRITE1_PRECISION_32 (0<<23) > -#define DDL_SPRITE1_SHIFT 16 > -#define DDL_SPRITE0_PRECISION_64 (1<<15) > -#define DDL_SPRITE0_PRECISION_32 (0<<15) > -#define DDL_SPRITE0_SHIFT 8 > +#define DDL_SPRITE_PRECISION_64(sprite) (1<<(15+8*(sprite))) > +#define DDL_SPRITE_PRECISION_32(sprite) (0<<(15+8*(sprite))) > +#define DDL_SPRITE_SHIFT(sprite) (8+8*(sprite)) > #define DDL_PLANE_PRECISION_64 (1<<7) > #define DDL_PLANE_PRECISION_32 (0<<7) > #define DDL_PLANE_SHIFT 0 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 86d6048..974aeea 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -1500,6 +1500,37 @@ static void cherryview_update_wm(struct drm_crtc *crtc) > intel_set_memory_cxsr(dev_priv, true); > } > > +static void valleyview_update_sprite_wm(struct drm_plane *plane, > + struct drm_crtc *crtc, > + uint32_t sprite_width, > + uint32_t sprite_height, > + int pixel_size, > + bool enabled, bool scaled) > +{ > + struct drm_device *dev = crtc->dev; > + struct drm_i915_private *dev_priv = dev->dev_private; > + int pipe = to_intel_plane(plane)->pipe; > + int sprite = to_intel_plane(plane)->plane; > + int drain_latency; > + int plane_prec; > + int sprite_dl; > + int prec_mult; > + > + sprite_dl = I915_READ(VLV_DDL(pipe)) & > ~(DDL_SPRITE_PRECISION_64(sprite) | > + (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); > + > + if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, > + &drain_latency)) { > + plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ? > + DDL_SPRITE_PRECISION_64(sprite) : > + DDL_SPRITE_PRECISION_32(sprite); > + sprite_dl |= plane_prec | > + (drain_latency << DDL_SPRITE_SHIFT(sprite)); > + } > + > + I915_WRITE(VLV_DDL(pipe), sprite_dl); > +} > + > static void g4x_update_wm(struct drm_crtc *crtc) > { > struct drm_device *dev = crtc->dev; > @@ -7231,10 +7262,12 @@ void intel_init_pm(struct drm_device *dev) > dev_priv->display.init_clock_gating = > gen8_init_clock_gating; > } else if (IS_CHERRYVIEW(dev)) { > dev_priv->display.update_wm = cherryview_update_wm; > + dev_priv->display.update_sprite_wm = > valleyview_update_sprite_wm; > dev_priv->display.init_clock_gating = > cherryview_init_clock_gating; > } else if (IS_VALLEYVIEW(dev)) { > dev_priv->display.update_wm = valleyview_update_wm; > + dev_priv->display.update_sprite_wm = > valleyview_update_sprite_wm; > dev_priv->display.init_clock_gating = > valleyview_init_clock_gating; > } else if (IS_PINEVIEW(dev)) { > -- > 1.7.9.5 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
