So that we write them at ring initialization and thus have them applied correctly after reset/resume.
Signed-off-by: Mika Kuoppala <[email protected]> --- drivers/gpu/drm/i915/i915_reg.h | 2 +- drivers/gpu/drm/i915/intel_pm.c | 61 +------------------ drivers/gpu/drm/i915/intel_ringbuffer.c | 100 ++++++++++++++++++++++++++++++++ 3 files changed, 102 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index b98138d..99cd494 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -4818,7 +4818,7 @@ enum punit_power_well { /* GEN7 chicken */ #define GEN7_COMMON_SLICE_CHICKEN1 0x7010 -# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26)) +# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC (1<<10) #define COMMON_SLICE_CHICKEN2 0x7014 # define GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE (1<<0) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 675e8a2..d8151a7 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -5712,7 +5712,7 @@ static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); /* - * WaVSThreadDispatchOverride:ivb,vlv + * WaVSThreadDispatchOverride:vlv * * This actually overrides the dispatch * mode for all thread types. @@ -5866,73 +5866,14 @@ static void ivybridge_init_clock_gating(struct drm_device *dev) I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); - /* WaDisableEarlyCull:ivb */ - I915_WRITE(_3D_CHICKEN3, - _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); - - /* WaDisableBackToBackFlipFix:ivb */ - I915_WRITE(IVB_CHICKEN3, - CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | - CHICKEN3_DGMG_DONE_FIX_DISABLE); - - /* WaDisablePSDDualDispatchEnable:ivb */ - if (IS_IVB_GT1(dev)) - I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, - _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); - - /* WaDisable_RenderCache_OperationalFlush:ivb */ - I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); - - /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ - I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, - GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); - - /* WaApplyL3ControlAndL3ChickenMode:ivb */ - I915_WRITE(GEN7_L3CNTLREG1, - GEN7_WA_FOR_GEN7_L3_CONTROL); - I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, - GEN7_WA_L3_CHICKEN_MODE); - if (IS_IVB_GT1(dev)) - I915_WRITE(GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); - else { - /* must write both registers */ - I915_WRITE(GEN7_ROW_CHICKEN2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); - I915_WRITE(GEN7_ROW_CHICKEN2_GT2, - _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); - } - - /* WaForceL3Serialization:ivb */ - I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & - ~L3SQ_URB_READ_CAM_MATCH_DISABLE); - - /* - * According to the spec, bit 13 (RCZUNIT) must be set on IVB. - * This implements the WaDisableRCZUnitClockGating:ivb workaround. - */ - I915_WRITE(GEN6_UCGCTL2, - GEN6_RCZUNIT_CLOCK_GATE_DISABLE); - - /* This is required by WaCatErrorRejectionIssue:ivb */ - I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, - I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | - GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); - g4x_disable_trickle_feed(dev); - gen7_setup_fixed_func_scheduler(dev_priv); - if (0) { /* causes HiZ corruption on ivb:gt1 */ /* enable HiZ Raw Stall Optimization */ I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); } - /* WaDisable4x2SubspanOptimization:ivb */ - I915_WRITE(CACHE_MODE_1, - _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); - /* * BSpec recommends 8x4 when MSAA is used, * however in practice 16x4 seems fastest. diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c index 4f336e23..abbb9f8 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.c +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c @@ -702,6 +702,21 @@ static int intel_ring_workarounds_emit(struct intel_engine_cs *ring) return 0; } +static void intel_ring_workarounds_write(struct intel_engine_cs *ring) +{ + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + struct i915_workarounds *w = &dev_priv->workarounds; + int i; + + for (i = 0; i < w->count; i++) { + I915_WRITE(dev_priv->workarounds.reg[i].addr, + dev_priv->workarounds.reg[i].value); + } + + DRM_DEBUG_DRIVER("Number of Workarounds written: %d\n", w->count); +} + static int wa_add(struct drm_i915_private *dev_priv, const u32 addr, const u32 val, const u32 mask) { @@ -734,6 +749,82 @@ static int wa_add(struct drm_i915_private *dev_priv, #define WA_WRITE(addr, val) WA_REG(addr, val, 0xffffffff) +static int ivb_init_workarounds(struct intel_engine_cs *ring) +{ + struct drm_device *dev = ring->dev; + struct drm_i915_private *dev_priv = dev->dev_private; + + /* WaDisableEarlyCull:ivb */ + WA_SET_BIT_MASKED(_3D_CHICKEN3, + _3D_CHICKEN_SF_DISABLE_OBJEND_CULL); + + /* WaDisableBackToBackFlipFix:ivb */ + WA_WRITE(IVB_CHICKEN3, + CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | + CHICKEN3_DGMG_DONE_FIX_DISABLE); + + /* WaDisablePSDDualDispatchEnable:ivb */ + if (IS_IVB_GT1(dev)) + WA_SET_BIT_MASKED(GEN7_HALF_SLICE_CHICKEN1, + GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE); + + /* WaDisable_RenderCache_OperationalFlush:ivb */ + WA_CLR_BIT_MASKED(CACHE_MODE_0_GEN7, RC_OP_FLUSH_ENABLE); + + /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ + WA_SET_BIT_MASKED(GEN7_COMMON_SLICE_CHICKEN1, + GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); + + /* WaApplyL3ControlAndL3ChickenMode:ivb */ + WA_WRITE(GEN7_L3CNTLREG1, + GEN7_WA_FOR_GEN7_L3_CONTROL); + WA_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, + GEN7_WA_L3_CHICKEN_MODE); + if (IS_IVB_GT1(dev)) { + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, + DOP_CLOCK_GATING_DISABLE); + } else { + /* must write both registers */ + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2, + DOP_CLOCK_GATING_DISABLE); + WA_SET_BIT_MASKED(GEN7_ROW_CHICKEN2_GT2, + DOP_CLOCK_GATING_DISABLE); + } + + /* WaForceL3Serialization:ivb */ + WA_CLR_BIT(GEN7_L3SQCREG4, L3SQ_URB_READ_CAM_MATCH_DISABLE); + + /* + * According to the spec, bit 13 (RCZUNIT) must be set on IVB. + * This implements the WaDisableRCZUnitClockGating:ivb workaround. + */ + WA_WRITE(GEN6_UCGCTL2, + GEN6_RCZUNIT_CLOCK_GATE_DISABLE); + + /* This is required by WaCatErrorRejectionIssue:ivb */ + WA_SET_BIT(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, + GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); + + /* + * WaVSThreadDispatchOverride:ivb + * + * This actually overrides the dispatch + * mode for all thread types. + */ + +#define SET_FF_SCHED(v) ((v) & ~GEN7_FF_SCHED_MASK) \ + | GEN7_FF_TS_SCHED_HW | GEN7_FF_VS_SCHED_HW | GEN7_FF_DS_SCHED_HW + + WA_REG(GEN7_FF_THREAD_MODE, + SET_FF_SCHED(I915_READ(GEN7_FF_THREAD_MODE)), GEN7_FF_SCHED_MASK); + + /* WaDisable4x2SubspanOptimization:ivb */ + WA_SET_BIT_MASKED(CACHE_MODE_1, + PIXEL_SUBSPAN_COLLECT_OPT_DISABLE); + + return 0; +} + static int bdw_init_workarounds(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; @@ -815,11 +906,20 @@ static int init_workarounds_ring(struct intel_engine_cs *ring) { struct drm_device *dev = ring->dev; struct drm_i915_private *dev_priv = dev->dev_private; + int ret; WARN_ON(ring->id != RCS); dev_priv->workarounds.count = 0; + if (IS_IVYBRIDGE(dev)) { + ret = ivb_init_workarounds(ring); + if (ret) + return ret; + + intel_ring_workarounds_write(ring); + } + if (IS_BROADWELL(dev)) return bdw_init_workarounds(ring); -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
