From: Clint Taylor <clinton.a.tay...@intel.com>
port_clock was being incorrectly computed and WRPLL was incorrectly
programmed for pixel doubled modes using a 27.027MHz pixel clock.
port_clock was set to 27.026 resulting in an output pixel clock
matching 27.000MHz. Since there is no way to correctly half the 27.027
frequency as an integer just set port_clock to 27027 for these modes.
Signed-off-by: Clint Taylor <clinton.a.tay...@intel.com>
---
drivers/gpu/drm/i915/intel_hdmi.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c
b/drivers/gpu/drm/i915/intel_hdmi.c
index 29ec153..a0786d6 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -933,6 +933,11 @@ bool intel_hdmi_compute_config(struct intel_encoder
*encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) {
pipe_config->pixel_multiplier = 2;
+
+ /* Fix up port_clock since 27027 is not divisible by 2 */
+ if (pipe_config->adjusted_mode.crtc_clock == 13513) {
+ pipe_config->port_clock = 27027;
+ }
}
if (intel_hdmi->color_range)
--
1.7.9.5
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