For Dual Link MIPI Panels, both Port A and Port C should be enabled
during the MIPI encoder enabling sequence. Similarly, during the
disabling sequence, both ports needs to be disabled.
Signed-off-by: Gaurav K Singh <gaurav.k.si...@intel.com>
Signed-off-by: Shobhit Kumar <shobhit.ku...@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 1 +
drivers/gpu/drm/i915/intel_dsi.c | 55 ++++++++++++++++++++++------
drivers/gpu/drm/i915/intel_dsi.h | 1 +
drivers/gpu/drm/i915/intel_dsi_panel_vbt.c | 1 +
4 files changed, 47 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 021f72b..b2fc92b 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6403,6 +6403,7 @@ enum punit_power_well {
#define DPI_ENABLE (1 << 31) /* A + B */
#define MIPIA_MIPI4DPHY_DELAY_COUNT_SHIFT 27
#define MIPIA_MIPI4DPHY_DELAY_COUNT_MASK (0xf << 27)
+#define DUAL_LINK_MODE_SHIFT 26
#define DUAL_LINK_MODE_MASK (1 << 26)
#define DUAL_LINK_MODE_FRONT_BACK (0 << 26)
#define DUAL_LINK_MODE_PIXEL_ALTERNATIVE (1 << 26)
diff --git a/drivers/gpu/drm/i915/intel_dsi.c b/drivers/gpu/drm/i915/intel_dsi.c
index 69828c3..2c30b61 100644
--- a/drivers/gpu/drm/i915/intel_dsi.c
+++ b/drivers/gpu/drm/i915/intel_dsi.c
@@ -108,14 +108,33 @@ static void intel_dsi_port_enable(struct intel_encoder
*encoder)
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+ enum pipe pipe = intel_crtc->pipe;
int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe);
- u32 temp;
-
- /* assert ip_tg_enable signal */
- temp = I915_READ(MIPI_PORT_CTRL(port)) & ~LANE_CONFIGURATION_MASK;
- temp = temp | intel_dsi->port_bits;
- I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
- POSTING_READ(MIPI_PORT_CTRL(port));
+ u32 temp, port_control = 0;
+
+ if (intel_dsi->dual_link) {
+ port_control = (intel_dsi->dual_link - 1)
+ << DUAL_LINK_MODE_SHIFT;
+ port_control |= pipe ? LANE_CONFIGURATION_DUAL_LINK_B :
+ LANE_CONFIGURATION_DUAL_LINK_A;
+ /*For Port A */
+ temp = I915_READ(MIPI_PORT_CTRL(0));
+ temp = temp | port_control;
+ I915_WRITE(MIPI_PORT_CTRL(0), temp | DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(0));
+
+ /* For Port C */
+ temp = I915_READ(MIPI_PORT_CTRL(1));
+ I915_WRITE(MIPI_PORT_CTRL(1), temp | DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(1));
+ } else {
+ /* assert ip_tg_enable signal */
+ temp = I915_READ(MIPI_PORT_CTRL(port)) &
+ ~LANE_CONFIGURATION_MASK;
+ temp = temp | intel_dsi->port_bits;
+ I915_WRITE(MIPI_PORT_CTRL(port), temp | DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(port));
+ }
}
static void intel_dsi_port_disable(struct intel_encoder *encoder)
@@ -123,13 +142,26 @@ static void intel_dsi_port_disable(struct intel_encoder
*encoder)
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
+ struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe);
u32 temp;
- /* de-assert ip_tg_enable signal */
- temp = I915_READ(MIPI_PORT_CTRL(port));
- I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
- POSTING_READ(MIPI_PORT_CTRL(port));
+ if (intel_dsi->dual_link) {
+ /*For Port A */
+ temp = I915_READ(MIPI_PORT_CTRL(0));
+ I915_WRITE(MIPI_PORT_CTRL(0), temp & ~DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(0));
+
+ /* For Port C */
+ temp = I915_READ(MIPI_PORT_CTRL(1));
+ I915_WRITE(MIPI_PORT_CTRL(1), temp & ~DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(1));
+ } else {
+ /* de-assert ip_tg_enable signal */
+ temp = I915_READ(MIPI_PORT_CTRL(port));
+ I915_WRITE(MIPI_PORT_CTRL(port), temp & ~DPI_ENABLE);
+ POSTING_READ(MIPI_PORT_CTRL(port));
+ }
}
static void intel_dsi_device_ready(struct intel_encoder *encoder)
@@ -505,6 +537,7 @@ static void intel_dsi_prepare(struct intel_encoder
*intel_encoder)
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct drm_display_mode *adjusted_mode =
&intel_crtc->config.adjusted_mode;
+ enum pipe pipe = intel_crtc->pipe;
int port = PIPE_MAPPED_TO_MIPI_PORT(intel_crtc->pipe);
unsigned int bpp = intel_crtc->config.pipe_bpp;
u32 val, tmp;
diff --git a/drivers/gpu/drm/i915/intel_dsi.h b/drivers/gpu/drm/i915/intel_dsi.h
index 587e71f..950ab41 100644
--- a/drivers/gpu/drm/i915/intel_dsi.h
+++ b/drivers/gpu/drm/i915/intel_dsi.h
@@ -101,6 +101,7 @@ struct intel_dsi {
u8 clock_stop;
u8 escape_clk_div;
+ u8 dual_link;
u32 port_bits;
u32 bw_timer;
u32 dphy_reg;
diff --git a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
index 051bfff..d424ebc 100644
--- a/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_panel_vbt.c
@@ -283,6 +283,7 @@ static bool generic_init(struct intel_dsi_device *dsi)
intel_dsi->lane_count = mipi_config->lane_cnt + 1;
intel_dsi->pixel_format = mipi_config->videomode_color_format << 7;
intel_dsi->port = 0;
+ intel_dsi->dual_link = mipi_config->dual_link;
if (intel_dsi->pixel_format == VID_MODE_FORMAT_RGB666)
bits_per_pixel = 18;
--
1.7.9.5
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