On Thu, Nov 20, 2014 at 02:22:08AM -0800, Rodrigo Vivi wrote: > This function was in use to check if PSR feature got enabled. > However on HSW and BDW we currently force psr exit by disabling > EDP_PSR_ENABLE bit at EDP_PSR_CTL(dev). So this function was actually > returning the active/inactive state that is different from the enable/disable > meaning and had the risk of false negative. > > But anyway this check with DRRS was dangerous, since DRRS could try to get > enabled > before PSR gets there. So let's just remove it for now. > A proper synchronization mechanism must be implemented later probably > using pipe config.
Patch changelog is missing. Not that important just for spelling fixes, but still nice to mention when that's really the only thing that's changed. -Daniel > > Cc: Daniel Vetter <[email protected]> > Reviewed-by: Durgadoss R <[email protected]> > Signed-off-by: Rodrigo Vivi <[email protected]> > --- > drivers/gpu/drm/i915/intel_dp.c | 9 ++------- > drivers/gpu/drm/i915/intel_drv.h | 1 - > drivers/gpu/drm/i915/intel_psr.c | 10 ---------- > 3 files changed, 2 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 46731da..5be6f5e 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -4761,14 +4761,9 @@ void intel_dp_set_drrs_state(struct drm_device *dev, > int refresh_rate) > } > > /* > - * FIXME: This needs proper synchronization with psr state. But really > - * hard to tell without seeing the user of this function of this code. > - * Check locking and ordering once that lands. > + * FIXME: This needs proper synchronization with psr state for some > + * platforms that cannot have PSR and DRRS enabled at the same time. > */ > - if (INTEL_INFO(dev)->gen < 8 && intel_psr_is_enabled(dev)) { > - DRM_DEBUG_KMS("DRRS is disabled as PSR is enabled\n"); > - return; > - } > > encoder = intel_attached_encoder(&intel_connector->base); > intel_dp = enc_to_intel_dp(&encoder->base); > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index d1f9b63..7feded0 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1113,7 +1113,6 @@ void intel_backlight_unregister(struct drm_device *dev); > > > /* intel_psr.c */ > -bool intel_psr_is_enabled(struct drm_device *dev); > void intel_psr_enable(struct intel_dp *intel_dp); > void intel_psr_disable(struct intel_dp *intel_dp); > void intel_psr_invalidate(struct drm_device *dev, > diff --git a/drivers/gpu/drm/i915/intel_psr.c > b/drivers/gpu/drm/i915/intel_psr.c > index 843762a..576ad02 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -61,16 +61,6 @@ static bool is_edp_psr(struct intel_dp *intel_dp) > return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED; > } > > -bool intel_psr_is_enabled(struct drm_device *dev) > -{ > - struct drm_i915_private *dev_priv = dev->dev_private; > - > - if (!HAS_PSR(dev)) > - return false; > - > - return I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE; > -} > - > static void intel_psr_write_vsc(struct intel_dp *intel_dp, > struct edp_vsc_psr *vsc_psr) > { > -- > 1.9.3 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
