On Thu, Feb 05, 2015 at 10:47:21AM +0000, Nick Hoath wrote: > From: "Hoath, Nicholas" <[email protected]> > > Add stepping check for WaDisableSDEUnitClockGating. > > Signed-off-by: Nick Hoath <[email protected]>
Reviewed-by: Damien Lespiau <[email protected]> -- Damien > --- > drivers/gpu/drm/i915/intel_pm.c | 14 ++++++++------ > 1 file changed, 8 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 2b89aac..06d67fd 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -56,12 +56,14 @@ static void gen9_init_clock_gating(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > > - /* > - * WaDisableSDEUnitClockGating:skl > - * This seems to be a pre-production w/a. > - */ > - I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > - GEN8_SDEUNIT_CLOCK_GATE_DISABLE); > + if (INTEL_REVID(dev) == SKL_A0_REVID) { > + /* > + * WaDisableSDEUnitClockGating:skl > + * This seems to be a pre-production w/a. > + */ > + I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | > + GEN8_SDEUNIT_CLOCK_GATE_DISABLE); > + } > > /* Wa4x4STCOptimizationDisable:skl */ > I915_WRITE(CACHE_MODE_1, > -- > 2.1.1 > _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
