Re: [Intel-gfx] [PATCH 9/9] drm/i915: gen5+ can have FBC with multiple pipes

[shuang . he]

Tested-By: PRC QA PRTS (Patch Regression Test System Contact: 
shuang...@intel.com)
Task id: 5734
-------------------------------------Summary-------------------------------------
Platform          Delta          drm-intel-nightly          Series Applied
PNV                                  282/283              282/283
ILK                                  308/315              308/315
SNB              +1-1              340/346              340/346
IVB                 -1              378/384              377/384
BYT                                  296/296              296/296
HSW              +1                 421/428              422/428
BDW                                  318/333              318/333
-------------------------------------Detailed-------------------------------------
Platform  Test                                drm-intel-nightly          Series 
Applied
 SNB  igt_kms_flip_dpms-vs-vblank-race-interruptible      DMESG_WARN(3, 
M22)PASS(2, M22)      DMESG_WARN(1, M22)
 SNB  igt_kms_pipe_crc_basic_read-crc-pipe-A      DMESG_WARN(1, M22)PASS(6, 
M22)      PASS(1, M22)
 IVB  igt_gem_pwrite_pread_snooped-copy-performance      DMESG_WARN(1, 
M34)PASS(5, M34)      DMESG_WARN(1, M34)
 HSW  igt_gem_storedw_loop_blt      DMESG_WARN(2, M20)PASS(3, M20)      PASS(1, 
M20)
Note: You need to pay more attention to line start with '*'
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