On 02/24/2015 05:36 PM, Ville Syrjälä wrote:
On Mon, Feb 23, 2015 at 03:55:56PM +0000, Tvrtko Ursulin wrote:
From: Damien Lespiau <[email protected]>

Skylake is able to scannout those tiling formats. We need to allow them
in the ADDFB ioctl and tell the harware about it.

v2: Rebased for addfb2 interface. (Tvrtko Ursulin)
v3: Rebased for fb modifier changes. (Tvrtko Ursulin)
v4: Don't allow Y tiled fbs just yet. (Tvrtko Ursulin)
v5: Check for stride alignment and max pitch. (Tvrtko Ursulin)
v6: Simplify maximum pitch check. (Ville Syrjälä)
v7: Drop the gen9 check since requirements are no different. (Ville Syrjälä)

Signed-off-by: Damien Lespiau <[email protected]>
Signed-off-by: Tvrtko Ursulin <[email protected]>
Cc: Ville Syrjälä <[email protected]>
---
  drivers/gpu/drm/i915/intel_display.c | 115 ++++++++++++++++++++++++-----------
  drivers/gpu/drm/i915/intel_drv.h     |   2 +
  drivers/gpu/drm/i915/intel_sprite.c  |  18 ++++--
  3 files changed, 95 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c 
b/drivers/gpu/drm/i915/intel_display.c
index 6e70748..a523d84 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2728,6 +2728,34 @@ static void ironlake_update_primary_plane(struct 
drm_crtc *crtc,
        POSTING_READ(reg);
  }

+u32 intel_fb_stride_alignment(struct drm_device *dev, uint64_t fb_modifier,
+                             uint32_t pixel_format)
+{
+       u32 bits_per_pixel = drm_format_plane_cpp(pixel_format, 0) * 8;
+
+       /*
+        * The stride is either expressed as a multiple of 64 bytes
+        * chunks for linear buffers or in number of tiles for tiled
+        * buffers.
+        */
+       switch (fb_modifier) {
+       case DRM_FORMAT_MOD_NONE:
+               return 64;
+       case I915_FORMAT_MOD_X_TILED:

if (gen2)
        return 128;

Okay I'll add it blindly, but again, I failed to find this in existing code.

+               return 512;
+       case I915_FORMAT_MOD_Y_TILED:
+               return 128;

In theory we could check gen2 and HAS_128_BYTE_Y_TILING() here, but
since old platforms didn't do Y tiled scanout anyway that's not really
needed. But maybe toss in a comment about that so that people don't
start wondering why this doesn't care about that stuff?

Will do.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
[email protected]
http://lists.freedesktop.org/mailman/listinfo/intel-gfx

Reply via email to