On Thu, Mar 12, 2015 at 12:09:50PM +0000, Thomas Wood wrote: > On 10 March 2015 at 21:17, <jeff.mc...@intel.com> wrote: > > From: Jeff McGee <jeff.mc...@intel.com> > > > > New test pm_sseu is intended for any subtest related to the > > slice/subslice/EU power gating feature. The sole initial subtest, > > 'full-enable', confirms that the slice/subslice/EU state is at > > full enablement when the render engine is active. Starting with > > Gen9 SKL, the render power gating feature can leave SSEU in a > > partially enabled state upon resumption of render work unless > > explicit action is taken. > > Please add a short description to the test using the > IGT_TEST_DESCRIPTION macro, so that it is included in the > documentation and help output. >
Hi Thomas. I have posted v2 patches to address this and your other comments. Can you please have a second look? Thanks -Jeff _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/intel-gfx
