On Wed, Apr 29, 2015 at 11:56:41AM +0530, Sivakumar Thulasimani wrote:
> Reviewed-by: Sivakumar Thulasimani <[email protected]>
>
> On 4/29/2015 11:47 AM, Mika Kahola wrote:
> >This is a first of series patches that optimize DP link
> >training. The first patch is for eDP only where we reuse
> >the previously trained link training values from cache
> >i.e. voltage swing and pre-emphasis levels.
> >
> >In case we are not able to train the link by reusing
> >the known values, the link training parameters are set
> >to zero and training is restarted.
> >
> >V2:
> >- flag that indicates if DP link is trained and valid
> > renamed from 'link_trained' to 'train_set_valid'
> >- removed routine 'intel_dp_reuse_link_train'
> >
> >V3:
> >- rebased against the latest drm-intel-nightly
> >
> >V4:
> >- removed HPD long pulse handling for eDP case to clear the
> > flag that indicates to reuse the current link training
> > parameters. (based on Sivakumar's comment)
> >
> >Signed-off-by: Mika Kahola <[email protected]>
Both merged, with an s/DP/eDP/ on this one to make the different scope of
the 2 patches clear. Two patches with the same summary is confusing ;-)
Thanks, Daniel
> >---
> > drivers/gpu/drm/i915/intel_dp.c | 27 ++++++++++++++++++++++++---
> > drivers/gpu/drm/i915/intel_drv.h | 1 +
> > 2 files changed, 25 insertions(+), 3 deletions(-)
> >
> >diff --git a/drivers/gpu/drm/i915/intel_dp.c
> >b/drivers/gpu/drm/i915/intel_dp.c
> >index 937ba31..e0b35cb 100644
> >--- a/drivers/gpu/drm/i915/intel_dp.c
> >+++ b/drivers/gpu/drm/i915/intel_dp.c
> >@@ -3547,7 +3547,8 @@ static bool
> > intel_dp_reset_link_train(struct intel_dp *intel_dp, uint32_t *DP,
> > uint8_t dp_train_pat)
> > {
> >- memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> >+ if (!intel_dp->train_set_valid)
> >+ memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
> > intel_dp_set_signal_levels(intel_dp, DP);
> > return intel_dp_set_link_train(intel_dp, DP, dp_train_pat);
> > }
> >@@ -3660,6 +3661,23 @@ intel_dp_start_link_train(struct intel_dp *intel_dp)
> > break;
> > }
> >+ /*
> >+ * if we used previously trained voltage and pre-emphasis values
> >+ * and we don't get clock recovery, reset link training values
> >+ */
> >+ if (intel_dp->train_set_valid) {
> >+ DRM_DEBUG_KMS("clock recovery not ok, reset");
> >+ /* clear the flag as we are not reusing train set */
> >+ intel_dp->train_set_valid = false;
> >+ if (!intel_dp_reset_link_train(intel_dp, &DP,
> >+ DP_TRAINING_PATTERN_1 |
> >+
> >DP_LINK_SCRAMBLING_DISABLE)) {
> >+ DRM_ERROR("failed to enable link training\n");
> >+ return;
> >+ }
> >+ continue;
> >+ }
> >+
> > /* Check to see if we've tried the max voltage */
> > for (i = 0; i < intel_dp->lane_count; i++)
> > if ((intel_dp->train_set[i] &
> > DP_TRAIN_MAX_SWING_REACHED) == 0)
> >@@ -3737,6 +3755,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> > /* Make sure clock is still ok */
> > if (!drm_dp_clock_recovery_ok(link_status,
> > intel_dp->lane_count)) {
> >+ intel_dp->train_set_valid = false;
> > intel_dp_start_link_train(intel_dp);
> > intel_dp_set_link_train(intel_dp, &DP,
> > training_pattern |
> >@@ -3752,6 +3771,7 @@ intel_dp_complete_link_train(struct intel_dp *intel_dp)
> > /* Try 5 times, then try clock recovery if that fails */
> > if (tries > 5) {
> >+ intel_dp->train_set_valid = false;
> > intel_dp_start_link_train(intel_dp);
> > intel_dp_set_link_train(intel_dp, &DP,
> > training_pattern |
> >@@ -3773,9 +3793,10 @@ intel_dp_complete_link_train(struct intel_dp
> >*intel_dp)
> > intel_dp->DP = DP;
> >- if (channel_eq)
> >+ if (channel_eq) {
> >+ intel_dp->train_set_valid = is_edp(intel_dp);
> > DRM_DEBUG_KMS("Channel EQ done. DP Training successful\n");
> >-
> >+ }
> > }
> > void intel_dp_stop_link_train(struct intel_dp *intel_dp)
> >diff --git a/drivers/gpu/drm/i915/intel_drv.h
> >b/drivers/gpu/drm/i915/intel_drv.h
> >index 43fe003..94197bd 100644
> >--- a/drivers/gpu/drm/i915/intel_drv.h
> >+++ b/drivers/gpu/drm/i915/intel_drv.h
> >@@ -736,6 +736,7 @@ struct intel_dp {
> > bool has_aux_irq,
> > int send_bytes,
> > uint32_t aux_clock_divider);
> >+ bool train_set_valid;
> > /* Displayport compliance testing */
> > unsigned long compliance_test_type;
>
> --
> regards,
> Sivakumar
>
> _______________________________________________
> Intel-gfx mailing list
> [email protected]
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
http://blog.ffwll.ch
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