On 05/05/2015 07:17 AM, [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > On IBX the SDVO/HDMI register write may be masked when enabling the > port, so it may need to written twice. The HDMI code does this, but > the SDVO code does not. Add the workaround to the SDVO code as well. > > Signed-off-by: Ville Syrjälä <[email protected]> > --- > drivers/gpu/drm/i915/intel_sdvo.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_sdvo.c > b/drivers/gpu/drm/i915/intel_sdvo.c > index 0a06257..e3e9c98 100644 > --- a/drivers/gpu/drm/i915/intel_sdvo.c > +++ b/drivers/gpu/drm/i915/intel_sdvo.c > @@ -243,6 +243,14 @@ static void intel_sdvo_write_sdvox(struct intel_sdvo > *intel_sdvo, u32 val) > if (intel_sdvo->sdvo_reg == PCH_SDVOB) { > I915_WRITE(intel_sdvo->sdvo_reg, val); > POSTING_READ(intel_sdvo->sdvo_reg); > + /* > + * HW workaround, need to write this twice for issue > + * that may result in first write getting masked. > + */ > + if (HAS_PCH_IBX(dev)) { > + I915_WRITE(intel_sdvo->sdvo_reg, val); > + POSTING_READ(intel_sdvo->sdvo_reg); > + } > return; > } > >
This must be the missing fix to all our SDVO problems. (One can hope.) Reviewed-by: Jesse Barnes <[email protected]> _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
