On 5/26/2015 3:21 PM, Michel Thierry wrote:
When 48b is enabled, gen8_ppgtt_insert_entries needs to read the Page Map
Level 4 (PML4), before it selects which Page Directory Pointer (PDP)
it will write to.
Similarly, gen8_ppgtt_clear_range needs to get the correct PDP/PD range.
This patch was inspired by Ben's "Depend exclusively on map and
unmap_vma".
v2: Rebase after s/page_tables/page_table/.
v3: Remove unnecessary pdpe loop in gen8_ppgtt_clear_range_4lvl and use
clamp_pdp in gen8_ppgtt_insert_entries (Akash).
v4: Merge gen8_ppgtt_clear_range_4lvl into gen8_ppgtt_clear_range to
maintain symmetry with gen8_ppgtt_insert_entries (Akash).
v5: Do not mix pages and bytes in insert_entries (Akash).
Cc: Akash Goel <[email protected]>
Signed-off-by: Michel Thierry <[email protected]>
---
drivers/gpu/drm/i915/i915_gem_gtt.c | 51 +++++++++++++++++++++++++++++++------
drivers/gpu/drm/i915/i915_gem_gtt.h | 11 ++++++++
2 files changed, 54 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2b6ee8e..dbbf367 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -710,12 +725,31 @@ static void gen8_ppgtt_insert_entries(struct
i915_address_space *vm,
enum i915_cache_level cache_level,
u32 unused)
{
- struct i915_hw_ppgtt *ppgtt = container_of(vm, struct i915_hw_ppgtt,
base);
- struct i915_page_directory_pointer *pdp = &ppgtt->pdp; /* FIXME: 48b */
+ struct i915_hw_ppgtt *ppgtt =
+ container_of(vm, struct i915_hw_ppgtt, base);
struct sg_page_iter sg_iter;
__sg_page_iter_start(&sg_iter, pages->sgl, sg_nents(pages->sgl), 0);
- gen8_ppgtt_insert_pte_entries(pdp, &sg_iter, start, cache_level,
!HAS_LLC(vm->dev));
+
+ if (!USES_FULL_48BIT_PPGTT(vm->dev)) {
+ gen8_ppgtt_insert_pte_entries(&ppgtt->pdp, &sg_iter, start,
+ sg_nents(pages->sgl),
+ cache_level, !HAS_LLC(vm->dev));
+ } else {
+ struct i915_page_directory_pointer *pdp;
+ uint64_t templ4, pml4e;
+ uint64_t length = sg_nents(pages->sgl) << PAGE_SHIFT;
Actually, this should be:
uint64_t length = (uint64_t)sg_nents(pages->sgl) << PAGE_SHIFT;
Otherwise it will overflow if we're inserting 4GB at once.
+
+ gen8_for_each_pml4e(pdp, &ppgtt->pml4, start, length, templ4,
pml4e) {
+ uint64_t pdp_len = gen8_clamp_pdp(start, length) >>
PAGE_SHIFT;
+ uint64_t pdp_start = start;
+
+ gen8_ppgtt_insert_pte_entries(pdp, &sg_iter,
+ pdp_start, pdp_len,
+ cache_level,
+ !HAS_LLC(vm->dev));
+ }
+ }
}
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