On Fri, May 22, 2015 at 11:22:38AM +0300, Mika Kahola wrote: > From: Ville Syrjälä <[email protected]> > > Keep the cdclk maximum supported frequency around in dev_priv so that we > can verify certain things against it before actually changing the cdclk > frequency. > > For now only VLV/CHV have support changing cdclk frequency, so other > plarforms get to assume cdclk is fixed. > > Signed-off-by: Ville Syrjälä <[email protected]> > > v2: Rebased to the latest > v3: Rebased to the latest > > Reviewed-by: Mika Kahola <[email protected]> > > Author: Ville Syrjälä <[email protected]> > ---
Reviewed-by: Damien Lespiau <[email protected]> -- Damien > drivers/gpu/drm/i915/i915_drv.h | 2 +- > drivers/gpu/drm/i915/intel_display.c | 20 +++++++++++++++++++- > 2 files changed, 20 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 1038f5c..186a9e6 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1712,7 +1712,7 @@ struct drm_i915_private { > > unsigned int fsb_freq, mem_freq, is_ddr3; > unsigned int skl_boot_cdclk; > - unsigned int cdclk_freq; > + unsigned int cdclk_freq, max_cdclk_freq; > unsigned int hpll_freq; > > /** > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 1bdd2d7..51cbbca 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5750,6 +5750,21 @@ static int valleyview_get_vco(struct drm_i915_private > *dev_priv) > return vco_freq[hpll_freq] * 1000; > } > > +static void intel_update_max_cdclk(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + > + if (IS_VALLEYVIEW(dev)) { > + dev_priv->max_cdclk_freq = 400000; > + } else { > + /* otherwise assume cdclk is fixed */ > + dev_priv->max_cdclk_freq = dev_priv->cdclk_freq; > + } > + > + DRM_DEBUG_DRIVER("Max CD clock rate: %d kHz\n", > + dev_priv->max_cdclk_freq); > +} > + > static void intel_update_cdclk(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = dev->dev_private; > @@ -5771,6 +5786,9 @@ static void intel_update_cdclk(struct drm_device *dev) > */ > I915_WRITE(GMBUSFREQ_VLV, DIV_ROUND_UP(dev_priv->cdclk_freq, > 1000)); > } > + > + if (dev_priv->max_cdclk_freq == 0) > + intel_update_max_cdclk(dev); > } > > /* Adjust CDclk dividers to allow high res or save power if possible */ > @@ -6615,7 +6633,7 @@ static int intel_crtc_compute_config(struct intel_crtc > *crtc, > > /* FIXME should check pixel clock limits on all platforms */ > if (INTEL_INFO(dev)->gen < 4) { > - int clock_limit = dev_priv->cdclk_freq; > + int clock_limit = dev_priv->max_cdclk_freq; > > /* > * Enable pixel doubling when the dot clock > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
