Arun Siluvery <[email protected]> writes: > On 02/09/2015 12:29, Chris Wilson wrote: >> Fixes regression from >> commit f1afe24f0e736b9d7f2275e2b1504af3fe612f2a >> Author: Arun Siluvery <[email protected]> >> Date: Tue Aug 4 16:22:20 2015 +0100 >> >> drm/i915: Change SRM, LRM instructions to use correct length >> >> which forgot to account for the length bias when declaring the fixed >> length. >> >> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91844 >> Reported-by: Andreas Reis <[email protected]> >> Signed-off-by: Chris Wilson <[email protected]> >> Cc: Dave Gordon <[email protected]> >> Cc: Arun Siluvery <[email protected]> >> Cc: Mika Kuoppala <[email protected]> >> Cc: Daniel Vetter <[email protected]> >> --- >> drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c >> b/drivers/gpu/drm/i915/i915_cmd_parser.c >> index ad7d7ab76d3f..09932cab1a3f 100644 >> --- a/drivers/gpu/drm/i915/i915_cmd_parser.c >> +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c >> @@ -124,14 +124,14 @@ static const struct drm_i915_cmd_descriptor >> common_cmds[] = { >> CMD( MI_STORE_DWORD_INDEX, SMI, !F, 0xFF, R ), >> CMD( MI_LOAD_REGISTER_IMM(1), SMI, !F, 0xFF, W, >> .reg = { .offset = 1, .mask = 0x007FFFFC, .step = 2 } ), >> - CMD( MI_STORE_REGISTER_MEM, SMI, F, 1, W | B, >> + CMD( MI_STORE_REGISTER_MEM, SMI, F, 3, W | B, >> .reg = { .offset = 1, .mask = 0x007FFFFC }, >> .bits = {{ >> .offset = 0, >> .mask = MI_GLOBAL_GTT, >> .expected = 0, >> }}, ), >> - CMD( MI_LOAD_REGISTER_MEM, SMI, F, 1, W | B, >> + CMD( MI_LOAD_REGISTER_MEM, SMI, F, 3, W | B, >> .reg = { .offset = 1, .mask = 0x007FFFFC }, >> .bits = {{ >> .offset = 0, >> > My mistake, I should have verified on Gen7 hw.
Review is for mistakes, and review failed. -Mika _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
