On Fri, Sep 25, 2015 at 02:33:36PM +0100, Arun Siluvery wrote: > Signed-off-by: Arun Siluvery <[email protected]> > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index ab5ac5e..093a5e4 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -63,6 +63,10 @@ static void gen9_init_clock_gating(struct drm_device *dev) > /* WaDisableKillLogic:bxt,skl */ > I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | > ECOCHK_DIS_TLB); > + > + /* WaOCLCoherentLineFlush:skl,bxt */ > + I915_WRITE(GEN8_L3SQCREG4, (I915_READ(GEN8_L3SQCREG4) | > + GEN8_LQSC_FLUSH_COHERENT_LINES));
According to Bspec + w/a db this should be done for BDW too (actually BSpec shows it for BDW only?). If that's the case, then we should be able to kill gen8_emit_flush_coherentl3_wa(), no? Well, as long as someone goes and adds the DC flush to the normal post batch flush. > } > > static void skl_init_clock_gating(struct drm_device *dev) > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
