On 10/29/2015 12:25 PM, ville.syrj...@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrj...@linux.intel.com>
>
> ironlake_enaable_pch_transcoder() checks for CPT to see if it should
> enable the timing override chicken bit, but
> ironlake_disable_pch_transcoder() checks for !IBX to see if it should
> clear the same bit. Change ironlake_disable_pch_transcoder() to check
> for CPT as well to keep the two sides consistent.
>
> Signed-off-by: Ville Syrjälä <ville.syrj...@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index e820147..0d87a4e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2068,7 +2068,7 @@ static void ironlake_disable_pch_transcoder(struct
> drm_i915_private *dev_priv,
> if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
> DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe));
>
> - if (!HAS_PCH_IBX(dev)) {
> + if (HAS_PCH_CPT(dev)) {
> /* Workaround: Clear the timing override chicken bit again. */
> reg = TRANS_CHICKEN2(pipe);
> val = I915_READ(reg);
>
Reviewed-by: Jesse Barnes <jbar...@virtuousgeek.org>
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