On Mon, Dec 07, 2015 at 10:51:09AM -0800, Wayne Boyer wrote:
> Do some further clean up based on the initial review of
> drm/i915: Separate cherryview from valleyview.
>
> In this case, in i915_gem_alloc_context_obj() only call
> i915_gem_object_set_cache_level() for Ivy Bridge devices
> since later platforms don't have L3 control bits in the PTE.
>
> Cc: Ville Syrjälä <[email protected]>
> Cc: Rodrigo Vivi <[email protected]>
> Signed-off-by: Wayne Boyer <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_gem_context.c | 8 +++-----
> 1 file changed, 3 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_context.c
> b/drivers/gpu/drm/i915/i915_gem_context.c
> index 4b1161d..e4de433 100644
> --- a/drivers/gpu/drm/i915/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/i915_gem_context.c
> @@ -185,12 +185,10 @@ i915_gem_alloc_context_obj(struct drm_device *dev,
> size_t size)
> /*
> * Try to make the context utilize L3 as well as LLC.
> *
> - * On VLV we don't have L3 controls in the PTEs so we
> - * shouldn't touch the cache level, especially as that
> - * would make the object snooped which might have a
> - * negative performance impact.
> + * This is only applicable for Ivy Bridge devices since
> + * later platforms don't have L3 control bits in the PTE.
> */
> - if (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) &&
> !IS_CHERRYVIEW(dev)) {
> + if (IS_IVYBRIDGE(dev)) {
This would actually change the snoop setting on BXT, but that
should be fine since BXT still has the GTT -> PAT 0 thing which
means we get snooping anyway IIRC.
Imre, we discussed this stuff at some point, and I hope I'm not
forgetting something crucial here that would break BXT. Probably best
if you sanity check my thinking here...
We should probably mention this PAT 0 business in a comment somewhere
here since it's a very easy thing to miss.
> ret = i915_gem_object_set_cache_level(obj, I915_CACHE_L3_LLC);
> /* Failure shouldn't ever happen this early */
> if (WARN_ON(ret)) {
> --
> 2.6.3
--
Ville Syrjälä
Intel OTC
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