I'm working on getting our intel driver cleaned up under Haiku. i965 was working, however I have run into a few strange issues with the LVDS control changing on it's own after setting after my rewrite.
(panel control *is* unlocked via 0xabcd0000) Our intel_extreme rework code in-case anyone has the time to *really* dig in. https://github.com/kallisti5/haiku/tree/intel-extreme/src/add-ons/accelerants/intel_extreme Intel i965 mobile. LVDS display native 1440x900 Our ModeSetting (small snip of important code): KERN: intel_extreme: CALLED virtual status_t LVDSPort::SetDisplayMode(display_mode*, uint32) KERN: intel_extreme: SetDisplayMode: LVDS C-3 1440x900 KERN: intel_extreme: PLL limits, min: p 7 (p1 1, p2 14), n 1, m 70 (m1 8, m2 3) KERN: intel_extreme: PLL limits, max: p 98 (p1 8, p2 7), n 6, m 120 (m1 18, m2 7) KERN: intel_extreme: compute_pll_divisors: required MHz: 102 KERN: intel_extreme: compute_pll_divisors: found: 101.714 MHz, p = 21 (p1 = 3, p2 = 7), n = 4, m = 89 (m1 = 14, m2 = 7) KERN: intel_extreme: LVDS: dual channel KERN: intel_extreme: SetDisplayMode: LVDS Control: 0xc230833c KERN: intel_extreme: CALLED void Pipe::ConfigureTimings(const pll_divisors&, uint32, uint32) KERN: intel_extreme: SetDisplayMode: LVDS C didn't power on within 1000ms! KERN: intel_extreme: CALLED void Pipe:KERN: :Enable(display_mode*, addr_t) KERN: intel_extreme: CALLED void Pipe::_Enable(bool) KERN: intel_extreme: intel_set_display_mode: Port configuration completed successfully! KERN: intel_extreme: dump_registers: Taking register dump #1 KERN: intel_extreme: CALLED status_t intel_get_frame_buffer_config(frame_buffer_config*) We set LVDS control (0x00061180) to: 0xc230833c configure timings power on lvds enable pipe (assign to pipe b) dump registers. In that dump: LVDS (0x00061180): 0xc2300324 (enabled, pipe B, 18 bit, 1 channel) Thus... We set: 11000010001100001000001100111100 We later read: 11000010001100000000001100100100 ^^^^ CLKB B0,1,2 We set CLKB enabled. Later it's set to the "reserved" value We set B0,1,2 timing + color enabled, Later only timing is enabled I don't touch 0x00061180 after setting to 0xc230833c.. so I assume the GPU changes it to the invalid / reserved state? Here are a few short register dumps. LVDS is assigned pipe B and pipe B is enabled. The resulting screen is has vertical stripes on it with the correct mode. It feels like the B0,1,2 color being disabled could be impacting the every odd vertical line. (i'm using 27a2 below vs 2a02 as 2a02 isn't known to intel_reg to decode) $ ./intel_reg --mmio /var/run/media/kallisti5/Haiku/system/cache/tmp/ie-0001.bin --devid 27a2 read 0x60000 --count=8196 | egrep ")$" HTOTAL_A (0x00060000): 0x031f027f (640 active, 800 total) HBLANK_A (0x00060004): 0x03170287 (648 start, 792 end) HSYNC_A (0x00060008): 0x02ef028f (656 start, 752 end) VTOTAL_A (0x0006000c): 0x020c01df (480 active, 525 total) VBLANK_A (0x00060010): 0x020401e7 (488 start, 517 end) VSYNC_A (0x00060014): 0x01eb01e9 (490 start, 492 end) PIPEASRC (0x0006001c): 0x027f01df (640, 480) HTOTAL_B (0x00061000): 0x0747059f (1440 active, 1864 total) HBLANK_B (0x00061004): 0x0747059f (1440 start, 1864 end) HSYNC_B (0x00061008): 0x05ff05df (1504 start, 1536 end) VTOTAL_B (0x0006100c): 0x038f0383 (900 active, 912 total) VBLANK_B (0x00061010): 0x038f0383 (900 start, 912 end) VSYNC_B (0x00061014): 0x03890386 (903 start, 906 end) PIPEBSRC (0x0006101c): 0x059f0383 (1440, 900) ADPA (0x00061100): 0x40008c18 (disabled, pipe B, +hsync, +vsync) DVOA (0x00061120): 0x00000000 (disabled, pipe A, no stall, -hsync, -vsync) SDVOB (0x00061140): 0x8008001c (enabled, pipe A, stall disabled, detected) SDVOC (0x00061160): 0x00080018 (disabled, pipe A, stall disabled, not detected) LVDS (0x00061180): 0xc2300324 (enabled, pipe B, 18 bit, 1 channel) PP_STATUS (0x00061200): 0xc0000008 (on, ready, sequencing idle) PP_CONTROL (0x00061204): 0xabcd0003 (power target: on) $ ./intel_reg --mmio /var/run/media/kallisti5/Haiku/system/cache/tmp/ie-0001.bin --devid 27a2 read 0x6000 --count=8196 | egrep ")$" VCLK_DIVISOR_VGA0 (0x00006000): 0x00031108 (n = 3, m1 = 17, m2 = 8) VCLK_DIVISOR_VGA1 (0x00006004): 0x00031406 (n = 3, m1 = 20, m2 = 6) VCLK_POST_DIV (0x00006010): 0x00020002 (vga0 p1 = 4, p2 = 2, vga1 p1 = 2, p2 = 2) DPLL_A (0x00006014): 0x84800c00 (enabled, non-dvo, VGA, default clock, DAC/serial mode, p1 = 8, p2 = 10, SDVO mult 1) DPLL_B (0x00006018): 0x99040c00 (enabled, non-dvo, default clock, LVDS mode, p1 = 3, p2 = 7, SDVO mult 1) FPA0 (0x00006040): 0x00031108 (n = 3, m1 = 17, m2 = 8) FPA1 (0x00006044): 0x00031108 (n = 3, m1 = 17, m2 = 8) FPB0 (0x00006048): 0x00020c05 (n = 2, m1 = 12, m2 = 5) FPB1 (0x0000604c): 0x00020c05 (n = 2, m1 = 12, m2 = 5) DSPCLK_GATE_D (0x00006200): 0x00001000 (clock gates disabled: DPLUNIT) Anyone see anything too horribly wrong? Our driver was working on older chipsets but needed a major over-haul due to it not working with pch-split devices. (IvyBridge+) -- Alex _______________________________________________ Intel-gfx mailing list [email protected] http://lists.freedesktop.org/mailman/listinfo/intel-gfx
