[email protected] writes:
> From: Tim Gore <[email protected]>
>
> Add WaIncreaseDefaultTLBEntries:skl,bxt.
> This workaround provides significant perfromance boost
> for some OpenCL workloads by adjusting the L3_LRA_1_GPGPU
> register.
> This is for skl/bxt. Further patches will provide the
> workaround for other sku's.
>
> Signed-off-by: Tim Gore <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_gem_gtt.c | 4 ++++
> drivers/gpu/drm/i915/i915_reg.h | 2 ++
> 2 files changed, 6 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c
> b/drivers/gpu/drm/i915/i915_gem_gtt.c
> index be87318..6c8f936 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.c
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
> @@ -2145,6 +2145,10 @@ void gtt_write_workarounds(struct drm_device *dev)
> I915_WRITE(GEN8_L3_LRA_1_GPGPU,
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW);
> else if (IS_CHERRYVIEW(dev))
> I915_WRITE(GEN8_L3_LRA_1_GPGPU,
> GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV);
> + else if (IS_SKYLAKE(dev))
> + I915_WRITE(GEN8_L3_LRA_1_GPGPU,
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL);
> + else if (IS_BROXTON(dev))
> + I915_WRITE(GEN8_L3_LRA_1_GPGPU,
> GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT);
> }
You forgot to add these to the Wa comment.
-Mika
>
> int i915_ppgtt_init(struct drm_device *dev, struct i915_hw_ppgtt *ppgtt)
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 513e2980..b0516e2 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8163,5 +8163,7 @@ enum skl_disp_power_wells {
> #define GEN8_L3_LRA_1_GPGPU _MMIO(0x4dd4)
> #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_BDW 0x67F1427F /* max/min for
> LRA1/2 */
> #define GEN8_L3_LRA_1_GPGPU_DEFAULT_VALUE_CHV 0x5FF101FF /* max/min for
> LRA1/2 */
> +#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_SKL 0x67F1427F /* " "
> */
> +#define GEN9_L3_LRA_1_GPGPU_DEFAULT_VALUE_BXT 0x5FF101FF /* " "
> */
>
> #endif /* _I915_REG_H_ */
> --
> 1.9.1
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