On ke, 2016-02-17 at 21:41 +0200, [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > Rather than assume the VGA dotclock is really the FDI based thing, > let's read out the real thing via iclkip, and after readout it'll > get to compare it with the FDI based number to make sure they're > in sync. > > Cc: Paulo Zanoni <[email protected]> > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/i915_reg.h | 8 ++++++-- > drivers/gpu/drm/i915/intel_crt.c | 4 ++++ > drivers/gpu/drm/i915/intel_display.c | 37 > ++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_drv.h | 1 + > 4 files changed, 48 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 3774870477c1..a5f2c6e2edb2 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7362,9 +7362,11 @@ enum skl_disp_power_wells { > /* SBI offsets */ > #define SBI_SSCDIVINTPHASE 0x0200 > #define SBI_SSCDIVINTPHASE6 0x0600 > -#define SBI_SSCDIVINTPHASE_DIVSEL_MASK ((0x7f)<<1) > +#define SBI_SSCDIVINTPHASE_DIVSEL_SHIFT 1 > +#define SBI_SSCDIVINTPHASE_DIVSEL_MASK (0x7f<<1) > #define SBI_SSCDIVINTPHASE_DIVSEL(x) ((x)<<1) > -#define SBI_SSCDIVINTPHASE_INCVAL_MASK ((0x7f)<<8) > +#define SBI_SSCDIVINTPHASE_INCVAL_SHIFT 8 > +#define SBI_SSCDIVINTPHASE_INCVAL_MASK (0x7f<<8) > #define SBI_SSCDIVINTPHASE_INCVAL(x) ((x)<<8) > #define SBI_SSCDIVINTPHASE_DIR(x) ((x)<<15) > #define SBI_SSCDIVINTPHASE_PROPAGATE (1<<0) > @@ -7374,6 +7376,8 @@ enum skl_disp_power_wells { > #define SBI_SSCCTL_PATHALT (1<<3) > #define SBI_SSCCTL_DISABLE (1<<0) > #define SBI_SSCAUXDIV6 0x0610 > +#define SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT 4 > +#define SBI_SSCAUXDIV_FINALDIV2SEL_MASK (1<<4) > #define SBI_SSCAUXDIV_FINALDIV2SEL(x) ((x)<<4) > #define SBI_DBUFF0 0x2a00 > #define SBI_GEN0 0x1f00 > diff --git a/drivers/gpu/drm/i915/intel_crt.c > b/drivers/gpu/drm/i915/intel_crt.c > index f4c88d93a164..08964bbd7c82 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -128,6 +128,8 @@ static void intel_crt_get_config(struct > intel_encoder *encoder, > static void hsw_crt_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > + struct drm_i915_private *dev_priv = to_i915(encoder- > >base.dev); > + > intel_ddi_get_config(encoder, pipe_config); > > pipe_config->base.adjusted_mode.flags &= > ~(DRM_MODE_FLAG_PHSYNC | > @@ -135,6 +137,8 @@ static void hsw_crt_get_config(struct > intel_encoder *encoder, > DRM_MODE_FLAG_PVSYNC | > DRM_MODE_FLAG_NVSYNC); > pipe_config->base.adjusted_mode.flags |= > intel_crt_get_flags(encoder); > + > + pipe_config->base.adjusted_mode.crtc_clock = > lpt_get_iclkip(dev_priv); > } > > /* Note: The caller is required to filter out dpms modes not > supported by the > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index 5e7b22a31098..43cae2f8016d 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4032,6 +4032,43 @@ static void lpt_program_iclkip(struct drm_crtc > *crtc) > I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE); > } > > +int lpt_get_iclkip(struct drm_i915_private *dev_priv) > +{ > + u32 divsel, phaseinc, auxdiv; > + u32 iclk_virtual_root_freq = 172800 * 1000; > + u32 iclk_pi_range = 64; > + u32 desired_divisor; > + u32 temp; > + > + if ((I915_READ(PIXCLK_GATE) & PIXCLK_GATE_UNGATE) == 0) > + return 0; > + > + mutex_lock(&dev_priv->sb_lock); > + > + temp = intel_sbi_read(dev_priv, SBI_SSCCTL6, SBI_ICLK); > + if (temp & SBI_SSCCTL_DISABLE) { > + mutex_unlock(&dev_priv->sb_lock); > + return 0; > + } > + > + temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6, > SBI_ICLK); > + divsel = (temp & SBI_SSCDIVINTPHASE_DIVSEL_MASK) >> > + SBI_SSCDIVINTPHASE_DIVSEL_SHIFT; > + phaseinc = (temp & SBI_SSCDIVINTPHASE_INCVAL_MASK) >> > + SBI_SSCDIVINTPHASE_INCVAL_SHIFT; > + > + temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6, SBI_ICLK); > + auxdiv = (temp & SBI_SSCAUXDIV_FINALDIV2SEL_MASK) >> > + SBI_SSCAUXDIV_FINALDIV2SEL_SHIFT; > + > + mutex_unlock(&dev_priv->sb_lock); > + > + desired_divisor = (divsel + 2) * iclk_pi_range + phaseinc; > + > + return DIV_ROUND_CLOSEST(iclk_virtual_root_freq, > + desired_divisor << auxdiv); > +} > + > static void ironlake_pch_transcoder_set_timings(struct intel_crtc > *crtc, > enum pipe > pch_transcoder) > { > diff --git a/drivers/gpu/drm/i915/intel_drv.h > b/drivers/gpu/drm/i915/intel_drv.h > index c25a8880b4e8..3b64c9b002a8 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1158,6 +1158,7 @@ struct intel_shared_dpll > *intel_get_shared_dpll(struct intel_crtc *crtc, > int vlv_force_pll_on(struct drm_device *dev, enum pipe pipe, > const struct dpll *dpll); > void vlv_force_pll_off(struct drm_device *dev, enum pipe pipe); > +int lpt_get_iclkip(struct drm_i915_private *dev_priv); > > /* modesetting asserts */ > void assert_panel_unlocked(struct drm_i915_private *dev_priv, _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
