From: Tom O'Rourke <Tom.O'[email protected]> i915.enable_slpc is used to override the default for slpc usage. The expected values are -1=auto, 0=disabled [default], 1=enabled.
slpc_enable_sanitize() converts i915.enable_slpc to either 0 or 1. Interpretation of default value is based on HAS_SLPC(), after slpc_version_check(). This function also enforces the requirement that guc_submission is required for slpc. intel_slpc_enabled() returns 1 if SLPC should be used. Suggested-by: Paulo Zanoni <[email protected]> Signed-off-by: Tom O'Rourke <Tom.O'[email protected]> --- drivers/gpu/drm/i915/i915_params.c | 6 ++++++ drivers/gpu/drm/i915/i915_params.h | 1 + drivers/gpu/drm/i915/intel_guc.h | 6 ++++++ drivers/gpu/drm/i915/intel_guc_loader.c | 17 +++++++++++++++++ 4 files changed, 30 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c index 278c9c4..1cee0ea 100644 --- a/drivers/gpu/drm/i915/i915_params.c +++ b/drivers/gpu/drm/i915/i915_params.c @@ -36,6 +36,7 @@ struct i915_params i915 __read_mostly = { .enable_dc = -1, .enable_fbc = -1, .enable_execlists = -1, + .enable_slpc = 0, .enable_hangcheck = true, .enable_ppgtt = -1, .enable_psr = -1, @@ -125,6 +126,11 @@ MODULE_PARM_DESC(enable_execlists, "Override execlists usage. " "(-1=auto [default], 0=disabled, 1=enabled)"); +module_param_named_unsafe(enable_slpc, i915.enable_slpc, int, 0400); +MODULE_PARM_DESC(enable_slpc, + "Override single-loop-power-controller (slpc) usage. " + "(-1=auto, 0=disabled [default], 1=enabled)"); + module_param_named_unsafe(enable_psr, i915.enable_psr, int, 0600); MODULE_PARM_DESC(enable_psr, "Enable PSR " "(0=disabled, 1=enabled - link mode chosen per-platform, 2=force link-standby mode, 3=force link-off mode) " diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h index bd5026b..3de9fb8 100644 --- a/drivers/gpu/drm/i915/i915_params.h +++ b/drivers/gpu/drm/i915/i915_params.h @@ -39,6 +39,7 @@ struct i915_params { int enable_fbc; int enable_ppgtt; int enable_execlists; + int enable_slpc; int enable_psr; unsigned int preliminary_hw_support; int disable_power_well; diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index b18f5c3..298e243 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -110,6 +110,12 @@ struct intel_guc { uint32_t last_seqno[GUC_MAX_ENGINES_NUM]; }; +static inline int intel_slpc_enabled(void) +{ + WARN_ON(i915.enable_slpc < 0); + return i915.enable_slpc; +} + /* intel_guc_loader.c */ extern void intel_guc_ucode_init(struct drm_device *dev); extern int intel_guc_ucode_load(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/intel_guc_loader.c b/drivers/gpu/drm/i915/intel_guc_loader.c index 22d7587..d63f358 100644 --- a/drivers/gpu/drm/i915/intel_guc_loader.c +++ b/drivers/gpu/drm/i915/intel_guc_loader.c @@ -116,6 +116,21 @@ static void direct_interrupts_to_guc(struct drm_i915_private *dev_priv) I915_WRITE(GUC_WD_VECS_IER, ~irqs); } +static void slpc_enable_sanitize(struct drm_device *dev) +{ + /* handle default case */ + if (i915.enable_slpc < 0) + i915.enable_slpc = HAS_SLPC(dev); + + /* slpc requires hardware support and compatible firmware */ + if (!HAS_SLPC(dev)) + i915.enable_slpc = 0; + + /* slpc requires guc submission */ + if (!i915.enable_guc_submission) + i915.enable_slpc = 0; +} + static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_fw) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -125,6 +140,8 @@ static void slpc_version_check(struct drm_device *dev, struct intel_guc_fw *guc_ info = (struct intel_device_info *) &dev_priv->info; info->has_slpc = 0; } + + slpc_enable_sanitize(dev); } static u32 get_gttype(struct drm_i915_private *dev_priv) -- 1.9.1 _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
