On Thu, 31 Mar 2016, Imre Deak <[email protected]> wrote: > On to, 2016-03-31 at 19:47 +0300, Kannan, Vandana wrote: >> > -----Original Message----- >> > From: Deak, Imre >> > Sent: Thursday, March 31, 2016 9:45 AM >> > To: Kannan, Vandana <[email protected]>; intel- >> > [email protected] >> > Cc: Nikula, Jani <[email protected]> >> > Subject: Re: [PATCH v2] drm/i915: BXT DDI PHY sequence BUN >> > >> > On to, 2016-03-31 at 22:40 +0530, Vandana Kannan wrote: >> > > According to the BSpec update, bit 7 of PORT_CL1CM_DW0 register >> > needs >> > > to be checked to ensure that the register is in accessible state. >> > > Also, based on a BSpec update, changing the timeout value to check >> > > iphypwrgood, from 10ms to wait for up to 100us. >> > > >> > > v2: use wait_for_us instead of the atomic call. >> > > >> > > Signed-off-by: Vandana Kannan <[email protected]> >> > > Reported-by: Philippe Lecluse <[email protected]> >> > > Cc: Deak, Imre <[email protected]> >> > > Cc: Nikula, Jani <[email protected]> >> > > --- >> > > drivers/gpu/drm/i915/i915_reg.h | 1 + >> > > drivers/gpu/drm/i915/intel_ddi.c | 15 +++++++++++++-- >> > > 2 files changed, 14 insertions(+), 2 deletions(-) >> > > >> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h >> > > b/drivers/gpu/drm/i915/i915_reg.h index 7dfc400..9a02bfc 100644 >> > > --- a/drivers/gpu/drm/i915/i915_reg.h >> > > +++ b/drivers/gpu/drm/i915/i915_reg.h >> > > @@ -1318,6 +1318,7 @@ enum skl_disp_power_wells { >> > > #define _PORT_CL1CM_DW0_A 0x162000 >> > > #define _PORT_CL1CM_DW0_BC 0x6C000 >> > > #define PHY_POWER_GOOD (1 << 16) >> > > +#define PHY_RESERVED (1 << 7) >> > > #define BXT_PORT_CL1CM_DW0(phy) _BXT_PHY((phy), >> > _PORT_CL1CM_DW0_BC, \ >> > > >> > > _PORT_CL1CM_DW0_A) >> > > >> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c >> > > b/drivers/gpu/drm/i915/intel_ddi.c >> > > index 62de9f4..05a5b3a 100644 >> > > --- a/drivers/gpu/drm/i915/intel_ddi.c >> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c >> > > @@ -2669,9 +2669,20 @@ static void broxton_phy_init(struct >> > drm_i915_private *dev_priv, >> > > val |= GT_DISPLAY_POWER_ON(phy); >> > > I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val); >> > > >> > > - /* Considering 10ms timeout until BSpec is updated */ >> > > - if (wait_for(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> > PHY_POWER_GOOD, 10)) >> > > + /* >> > > + * The PHY registers start out inaccessible and respond to reads >> > with >> > > + * all 1s. Eventually they become accessible as they power up, >> > > then >> > > + * the reserved bit will give the default 0. Poll on the >> > > reserved bit >> > > + * becoming 0 to find when the PHY is accessible. >> > > + * HW team confirmed that the time to reach phypowergood status >> > is >> > > + * anywhere between 50 us and 100us. >> > > + */ >> > > + if (wait_for_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> > > + PHY_RESERVED)) && >> > > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> > > + PHY_POWER_GOOD) == >> > PHY_POWER_GOOD)), 100)) { >> > > DRM_ERROR("timeout during PHY%d power on\n", phy); >> > >> > Thanks. This is still missing Jani's comment, that is reading out the >> > register >> > only once and applying a mask before comparing against >> > PHY_POWER_GOOD. >> > >> > --Imre >> > >> [Vandana] >> Oh! Thought he said its fine on an updated mail. > > Hm, if you check below, > >> >> " >> > > + if (wait_for_atomic_us(((!(I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> > > + PHY_RESERVED)) && >> > > + ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & >> > > + PHY_POWER_GOOD) == PHY_POWER_GOOD)), >> > > 100)) { >> > >> > Is there any reason why you'd need to do the read twice? Why not just >> > write it as: >> >
This is the condition I meant: >> > (I915_READ(BXT_PORT_CL1CM_DW0(phy)) & (PHY_RESERVED | PHY_POWER_GOOD)) >> > == PHY_POWER_GOOD >> >> AFAICT this should be fine. > > This just means what I also asked. I'd prefer this, since reading out the > register twice is redundant and makes the reader wonder why it was needed > in the first place. Exactly, so I wrote the condition as I would write it, and meant *it* should be fine, i.e. with just one read of BXT_PORT_CL1CM_DW0. BR, Jani. -- Jani Nikula, Intel Open Source Technology Center _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
