On Sat, Apr 09, 2016 at 11:14:44AM +0100, Chris Wilson wrote: > In order for the MI_SEMAPHORE_SIGNAL command to wait until after the > pipecontrol writing the signal value is complete, we have to pause the > CS inside the PIPE_CONTROL with the CS_STALL bit. > > Signed-off-by: Chris Wilson <[email protected]> > --- > drivers/gpu/drm/i915/intel_ringbuffer.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c > b/drivers/gpu/drm/i915/intel_ringbuffer.c > index 556924ee47f9..62d09cf2ea8f 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -1301,7 +1301,7 @@ static int gen8_rcs_signal(struct drm_i915_gem_request > *signaller_req, > intel_ring_emit(signaller, GFX_OP_PIPE_CONTROL(6)); > intel_ring_emit(signaller, PIPE_CONTROL_GLOBAL_GTT_IVB | > PIPE_CONTROL_QW_WRITE | > - PIPE_CONTROL_FLUSH_ENABLE); > + PIPE_CONTROL_CS_STALL);
Doesn't this just stall when parsing the pipe control? Shouldn't we intead make sure the post-sync write is issued before the semaphore is signalled? (pipe_control /w post-sync write + second pipe control w/ flush enable?) Unfortunately it looks like the hardware wouldn't like it if we used the option to signal the semaphore as a post-sync operation. > intel_ring_emit(signaller, lower_32_bits(gtt_offset)); > intel_ring_emit(signaller, upper_32_bits(gtt_offset)); > intel_ring_emit(signaller, seqno); > @@ -1454,7 +1454,6 @@ gen8_ring_sync(struct drm_i915_gem_request *waiter_req, > > intel_ring_emit(waiter, MI_SEMAPHORE_WAIT | > MI_SEMAPHORE_GLOBAL_GTT | > - MI_SEMAPHORE_POLL | > MI_SEMAPHORE_SAD_GTE_SDD); > intel_ring_emit(waiter, seqno); > intel_ring_emit(waiter, > -- > 2.8.0.rc3 > > _______________________________________________ > Intel-gfx mailing list > [email protected] > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel OTC _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
