On Wed, 20 Apr 2016 20:27:56 +0300
Imre Deak <imre.d...@intel.com> wrote:
> After suspend-to-ram or -disk we don't know what power state the display
> HW will be, DC0 or DC9 are both possible states, so reset the software
> DC state tracking in these cases. This gets rid of 'DC state mismatch'
> error messages during resuming from ram or disk where we expected to be
> in DC9 (as set by the suspend handler) but we are in DC0.
>
> Signed-off-by: Imre Deak <imre.d...@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 7 +++++--
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 25 ++++++++++++++++++++++---
> 3 files changed, 28 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 4dc2904..9f55631 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -867,10 +867,13 @@ static int i915_drm_resume_early(struct drm_device *dev)
>
> intel_uncore_early_sanitize(dev, true);
>
> - if (IS_BROXTON(dev))
> + if (IS_BROXTON(dev)) {
> + if (!dev_priv->suspended_to_idle)
> + gen9_sanitize_dc_state(dev_priv);
> bxt_disable_dc9(dev_priv);
> - else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
> + } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> hsw_disable_pc8(dev_priv);
> + }
>
> intel_uncore_sanitize(dev);
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index beed9e8..5464632 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1235,6 +1235,7 @@ bool broxton_cdclk_verify_state(struct drm_i915_private
> *dev_priv);
> void broxton_ddi_phy_init(struct drm_i915_private *dev_priv);
> void broxton_ddi_phy_uninit(struct drm_i915_private *dev_priv);
> void broxton_ddi_phy_verify_state(struct drm_i915_private *dev_priv);
> +void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
> void bxt_enable_dc9(struct drm_i915_private *dev_priv);
> void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> void skl_init_cdclk(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 06d14c4..329784e 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -492,10 +492,9 @@ static void gen9_write_dc_state(struct drm_i915_private
> *dev_priv,
> state, rewrites);
> }
>
> -static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t
> state)
> +static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> {
> - uint32_t val;
> - uint32_t mask;
> + u32 mask;
>
> mask = DC_STATE_EN_UPTO_DC5;
> if (IS_BROXTON(dev_priv))
> @@ -503,10 +502,30 @@ static void gen9_set_dc_state(struct drm_i915_private
> *dev_priv, uint32_t state)
> else
> mask |= DC_STATE_EN_UPTO_DC6;
>
> + return mask;
> +}
> +
> +void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + val = I915_READ(DC_STATE_EN) & gen9_dc_mask(dev_priv);
> +
> + DRM_DEBUG_KMS("Resetting DC state tracking from %02x to %02x\n",
> + dev_priv->csr.dc_state, val);
> + dev_priv->csr.dc_state =val;
Just a nit, but missing white space after '='
With that, Reviewed-by: Bob Paauwe <bob.j.paa...@intel.com>
> +}
> +
> +static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t
> state)
> +{
> + uint32_t val;
> + uint32_t mask;
> +
> if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
> state &= dev_priv->csr.allowed_dc_mask;
>
> val = I915_READ(DC_STATE_EN);
> + mask = gen9_dc_mask(dev_priv);
> DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
> val & mask, state);
>
--
--
Bob Paauwe
bob.j.paa...@intel.com
IOTG / PED Software Organization
Intel Corp. Folsom, CA
(916) 356-6193
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