On pe, 2016-05-13 at 23:41 +0300, [email protected] wrote: > From: Ville Syrjälä <[email protected]> > > Currently we're trying to guess which lcpll vco frequency is used > use based on the cdclk. That doesn't work for cdclk==540 since > both vco frequencies can generate a 540 Mhz output. Let's stop > guessing and just read the actual vco frequency from the > hardware. > > Signed-off-by: Ville Syrjälä <[email protected]>
Reviewed-by: Imre Deak <[email protected]> > --- > drivers/gpu/drm/i915/intel_display.c | 73 > ++++++++++++++++++----------------- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 --- > 2 files changed, 37 insertions(+), 42 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index c1b1632664a1..e65c3da744b0 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5551,31 +5551,35 @@ static int skl_calc_cdclk(int max_pixclk, int vco) > } > } > > -static const struct skl_cdclk_entry { > - unsigned int freq; > - unsigned int vco; > -} skl_cdclk_frequencies[] = { > - { .freq = 308570, .vco = 8640 }, > - { .freq = 337500, .vco = 8100 }, > - { .freq = 432000, .vco = 8640 }, > - { .freq = 450000, .vco = 8100 }, > - { .freq = 540000, .vco = 8100 }, > - { .freq = 617140, .vco = 8640 }, > - { .freq = 675000, .vco = 8100 }, > -}; > - > -unsigned int skl_cdclk_get_vco(unsigned int freq) > +static void > +skl_dpll0_update(struct drm_i915_private *dev_priv) > { > - unsigned int i; > - > - for (i = 0; i < ARRAY_SIZE(skl_cdclk_frequencies); i++) { > - const struct skl_cdclk_entry *e = &skl_cdclk_frequencies[i]; > + u32 val; > > - if (e->freq == freq) > - return e->vco; > + val = I915_READ(LCPLL1_CTL); > + if ((val & LCPLL_PLL_ENABLE) == 0) { > + dev_priv->skl_vco_freq = 0; > + return; > } > > - return 8100; > + val = I915_READ(DPLL_CTRL1); > + > + switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) { > + case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0): > + case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0): > + case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0): > + case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0): > + dev_priv->skl_vco_freq = 8100; > + break; > + case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0): > + case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0): > + dev_priv->skl_vco_freq = 8640; > + break; > + default: > + MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)); > + dev_priv->skl_vco_freq = 0; > + break; > + } > } > > static void > @@ -6614,43 +6618,40 @@ static int intel_crtc_compute_config(struct > intel_crtc *crtc, > static int skylake_get_display_clock_speed(struct drm_device *dev) > { > struct drm_i915_private *dev_priv = to_i915(dev); > - uint32_t lcpll1 = I915_READ(LCPLL1_CTL); > - uint32_t cdctl = I915_READ(CDCLK_CTL); > - uint32_t linkrate; > + uint32_t cdctl; > > - if (!(lcpll1 & LCPLL_PLL_ENABLE)) > - return 24000; /* 24MHz is the cd freq with NSSC ref */ > + skl_dpll0_update(dev_priv); > > - if ((cdctl & CDCLK_FREQ_SEL_MASK) == CDCLK_FREQ_540) > - return 540000; > + if (dev_priv->skl_vco_freq == 0) > + return 24000; /* 24MHz is the cd freq with NSSC ref */ > > - linkrate = (I915_READ(DPLL_CTRL1) & > - DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1; > + cdctl = I915_READ(CDCLK_CTL); > > - if (linkrate == DPLL_CTRL1_LINK_RATE_2160 || > - linkrate == DPLL_CTRL1_LINK_RATE_1080) { > - /* vco 8640 */ > + if (dev_priv->skl_vco_freq == 8640) { > switch (cdctl & CDCLK_FREQ_SEL_MASK) { > case CDCLK_FREQ_450_432: > return 432000; > case CDCLK_FREQ_337_308: > return 308570; > + case CDCLK_FREQ_540: > + return 540000; > case CDCLK_FREQ_675_617: > return 617140; > default: > - WARN(1, "Unknown cd freq selection\n"); > + MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); > } > } else { > - /* vco 8100 */ > switch (cdctl & CDCLK_FREQ_SEL_MASK) { > case CDCLK_FREQ_450_432: > return 450000; > case CDCLK_FREQ_337_308: > return 337500; > + case CDCLK_FREQ_540: > + return 540000; > case CDCLK_FREQ_675_617: > return 675000; > default: > - WARN(1, "Unknown cd freq selection\n"); > + MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK); > } > } > > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 43ba60b3662e..5391ab66b64d 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -1633,14 +1633,8 @@ static void intel_ddi_pll_init(struct drm_device *dev) > uint32_t val = I915_READ(LCPLL_CTL); > > if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) { > - int cdclk_freq; > - > - cdclk_freq = dev_priv->display.get_display_clock_speed(dev); > - dev_priv->skl_vco_freq = skl_cdclk_get_vco(cdclk_freq); > if (skl_sanitize_cdclk(dev_priv)) > DRM_DEBUG_KMS("Sanitized cdclk programmed by pre-os\n"); > - if (!(I915_READ(LCPLL1_CTL) & LCPLL_PLL_ENABLE)) > - DRM_ERROR("LCPLL1 is disabled\n"); > } else if (!IS_BROXTON(dev_priv)) { > /* > * The LCPLL register should be turned on by the BIOS. For now _______________________________________________ Intel-gfx mailing list [email protected] https://lists.freedesktop.org/mailman/listinfo/intel-gfx
