num_levels should be level+1, not level, else num_levels - 1 becomes
negative. This resulted in bogus watermarks being written to the first
255 levels like below:
[drm] Setting FIFO watermarks - C: plane=0, cursor=0, sprite0=0, sprite1=0, SR:
plane=0, cursor=0 level=255 cxsr=0
[drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR DVFS
request
[drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe C FIFO
underrun
[drm:chv_set_memory_dvfs [i915]] *ERROR* timed out waiting for Punit DDR DVFS
request
Testcase: kms_atomic_transition
Fixes: 262cd2e154c2 ("drm/i915: CHV DDR DVFS support and another watermark
rewrite")
Cc: [email protected]
Cc: Ville Syrjälä <[email protected]>
Signed-off-by: Maarten Lankhorst <[email protected]>
---
Urgent fix for watermark support. This is definitely a pre-requisite for this
series.
With this I've noticed that patch "[RFC 3/8] drm/i915/vlv: Move fifo_size from
intel_plane_wm_parameters to vlv_wm_state" introduces a regression with invalid
FIFO split.
I need to find out what's going wrong in that patch before this series can be
applied.
drivers/gpu/drm/i915/intel_pm.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 376c60b98515..8defdcc54529 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1148,7 +1148,7 @@ static void vlv_compute_wm(struct intel_crtc *crtc)
}
}
- wm_state->num_levels = level;
+ wm_state->num_levels = level + 1;
if (!wm_state->cxsr)
continue;
--
2.7.4
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