Moving all GPU features to the platform definition allows for
- standard place when adding new features from new platforms
- possible to see supported features when dumpig struct
definitions
Signed-off-by: Carlos Santa <carlos.sa...@intel.com>
---
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_pci.c | 5 +++++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8f5b9fd..06d2850 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -781,6 +781,7 @@ struct intel_csr {
func(has_aux_irq) sep \
func(has_gmbus_irq) sep \
func(has_fw_blc) sep \
+ func(has_hw_contexts) sep \
func(has_resource_streamer) sep \
func(has_pipe_cxsr) sep \
func(has_hotplug) sep \
@@ -2814,7 +2815,7 @@ struct drm_i915_cmd_table {
HAS_EDRAM(dev))
#define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
-#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
+#define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->has_hw_contexts)
#define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
#define USES_PPGTT(dev) (i915.enable_ppgtt)
#define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index b44d162..26ff54e 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -209,6 +209,7 @@ static const struct intel_device_info intel_ironlake_m_info
= {
.has_aux_irq = 1, \
.has_gmbus_irq = 1, \
.has_fw_blc = 1, \
+ .has_hw_contexts = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -232,6 +233,7 @@ static const struct intel_device_info
intel_sandybridge_m_info = {
.has_aux_irq = 1, \
.has_gmbus_irq = 1, \
.has_fw_blc = 1, \
+ .has_hw_contexts = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.has_llc = 1, \
GEN_DEFAULT_PIPEOFFSETS, \
@@ -268,6 +270,7 @@ static const struct intel_device_info
intel_ivybridge_q_info = {
.has_aux_irq = 1, \
.has_gmbus_irq = 1, \
.has_fw_blc = 1, \
+ .has_hw_contexts = 1, \
.need_gfx_hws = 1, .has_hotplug = 1, \
.ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
.display_mmio_offset = VLV_DISPLAY_BASE, \
@@ -349,6 +352,7 @@ static const struct intel_device_info intel_cherryview_info
= {
.has_aux_irq = 1,
.has_gmbus_irq = 1,
.has_fw_blc = 1,
+ .has_hw_contexts = 1,
.display_mmio_offset = VLV_DISPLAY_BASE,
GEN_CHV_PIPEOFFSETS,
CURSOR_OFFSETS,
@@ -391,6 +395,7 @@ static const struct intel_device_info intel_broxton_info = {
.has_aux_irq = 1,
.has_gmbus_irq = 1,
.has_fw_blc = 1,
+ .has_hw_contexts = 1,
GEN_DEFAULT_PIPEOFFSETS,
IVB_CURSOR_OFFSETS,
BDW_COLORS,
--
1.9.1
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