On Thu, Jul 28, 2016 at 12:12:27PM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
> - standard place when adding new features from new platforms
> - possible to see supported features when dumping struct
> definitions
>
> Signed-off-by: Carlos Santa <[email protected]>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/i915_pci.c | 4 ++++
> 2 files changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 28c7264..50062b6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -780,6 +780,7 @@ struct intel_csr {
> func(has_rc6) sep \
> func(has_rc6p) sep \
> func(has_dp_mst) sep \
> + func(has_aux_irq) sep \
> func(has_pipe_cxsr) sep \
> func(has_hotplug) sep \
> func(cursor_needs_physical) sep \
> @@ -2720,7 +2721,7 @@ struct drm_i915_cmd_table {
> * legacy irq no. is shared with another device. The kernel then disables
> that
> * interrupt source and so prevents the other device from working properly.
> */
> -#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
> +#define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->has_aux_irq)
These kind of flags I'm not sure will buy us anything. They're not
likely to change ever, so we're just forcing new platforms to add more
and more boilerplate to the feature structs/templates.
While I generally disklike negative flags, I'm almost tempted to say
that for stuff like this, it might be better. That is if we even want to
turn them into flags.
> #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
>
> /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 693943f..8780924 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -180,6 +180,7 @@ static const struct intel_device_info intel_pineview_info
> = {
> #define GEN5_FEATURES \
> .gen = 5, .num_pipes = 2, \
> .need_gfx_hws = 1, .has_hotplug = 1, \
> + .has_aux_irq = 1, \
> .ring_mask = RENDER_RING | BSD_RING, \
> GEN_DEFAULT_PIPEOFFSETS, \
> CURSOR_OFFSETS
> @@ -243,6 +244,7 @@ static const struct intel_device_info
> intel_ivybridge_q_info = {
> .has_psr = 1, \
> .has_runtime_pm = 1, \
> .has_rc6 = 1, \
> + .has_aux_irq = 1, \
> .need_gfx_hws = 1, .has_hotplug = 1, \
> .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
> .display_mmio_offset = VLV_DISPLAY_BASE, \
> @@ -321,6 +323,7 @@ static const struct intel_device_info
> intel_cherryview_info = {
> .has_runtime_pm = 1,
> .has_resource_streamer = 1,
> .has_rc6 = 1,
> + .has_aux_irq = 1,
> .display_mmio_offset = VLV_DISPLAY_BASE,
> GEN_CHV_PIPEOFFSETS,
> CURSOR_OFFSETS,
> @@ -357,6 +360,7 @@ static const struct intel_device_info intel_broxton_info
> = {
> .has_resource_streamer = 1,
> .has_rc6 = 1,
> .has_dp_mst = 1,
> + .has_aux_irq = 1,
> GEN_DEFAULT_PIPEOFFSETS,
> IVB_CURSOR_OFFSETS,
> BDW_COLORS,
> --
> 1.9.1
>
> _______________________________________________
> Intel-gfx mailing list
> [email protected]
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel OTC
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