On Tue, Aug 09, 2016 at 11:45:12AM -0700, Carlos Santa wrote:
> Moving all GPU features to the platform struct definition allows for
>       - standard place when adding new features from new platforms
>       - possible to see supported features when dumping struct
>         definitions
> 
> Signed-off-by: Carlos Santa <[email protected]>


Reviewed-by: Rodrigo Vivi <[email protected]>

> ---
>  drivers/gpu/drm/i915/i915_drv.h | 3 ++-
>  drivers/gpu/drm/i915/i915_pci.c | 5 +++++
>  2 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3ab63c0..14e8911 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -772,6 +772,7 @@ struct intel_csr {
>       func(has_fbc) sep \
>       func(has_psr) sep \
>       func(has_runtime_pm) sep \
> +     func(has_csr) sep \
>       func(has_pipe_cxsr) sep \
>       func(has_hotplug) sep \
>       func(cursor_needs_physical) sep \
> @@ -2774,7 +2775,7 @@ struct drm_i915_cmd_table {
>  #define HAS_RC6(dev)         (INTEL_INFO(dev)->gen >= 6)
>  #define HAS_RC6p(dev)                (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
>  
> -#define HAS_CSR(dev) (IS_GEN9(dev))
> +#define HAS_CSR(dev) (INTEL_INFO(dev)->has_csr)
>  
>  /*
>   * For now, anything with a GuC requires uCode loading, and then supports
> diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
> index 9d78836..21a3bc5 100644
> --- a/drivers/gpu/drm/i915/i915_pci.c
> +++ b/drivers/gpu/drm/i915/i915_pci.c
> @@ -301,12 +301,14 @@ static const struct intel_device_info 
> intel_skylake_info = {
>       BDW_FEATURES,
>       .is_skylake = 1,
>       .gen = 9,
> +     .has_csr = 1,
>  };
>  
>  static const struct intel_device_info intel_skylake_gt3_info = {
>       BDW_FEATURES,
>       .is_skylake = 1,
>       .gen = 9,
> +     .has_csr = 1,
>       .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> @@ -321,6 +323,7 @@ static const struct intel_device_info intel_broxton_info 
> = {
>       .has_fbc = 1,
>       .has_runtime_pm = 1,
>       .has_pooled_eu = 0,
> +     .has_csr = 1,
>       GEN_DEFAULT_PIPEOFFSETS,
>       IVB_CURSOR_OFFSETS,
>       BDW_COLORS,
> @@ -330,12 +333,14 @@ static const struct intel_device_info 
> intel_kabylake_info = {
>       BDW_FEATURES,
>       .is_kabylake = 1,
>       .gen = 9,
> +     .has_csr = 1,
>  };
>  
>  static const struct intel_device_info intel_kabylake_gt3_info = {
>       BDW_FEATURES,
>       .is_kabylake = 1,
>       .gen = 9,
> +     .has_csr = 1,
>       .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING | BSD2_RING,
>  };
>  
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
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