Re: [Intel-wired-lan] [PATCH v5 iwl-next 09/12] ice: Add support for E825-C TS PLL handling

[Kolacinski, Karol]

From: Aleksander Lobakin <aleksander.loba...@intel.com>
Date: Thu,  4 Apr 2024 13:11 +0200

[...]
> > +#define NAC_CGU_DWORD16_E825C 0x40
> > +union nac_cgu_dword16_e825c {
> > +     struct {
> > +             u32 synce_remndr : 6;
> > +             u32 synce_phlmt_en : 1;
> > +             u32 misc13 : 17;
> > +             u32 tspll_ck_refclkfreq : 8;
> > +     };
> > +     u32 val;
> > +};
> 
> Will this work on Big Endian systems?

I guess it won't, not sure about compiler behaviour.
It would probably work better with masks defined and le32_to_cpu().

[...]

Thanks,
Karol