From: Aleksander Lobakin <[email protected]>
Date: Thu, 4 Apr 2024 13:08 +0200
[...]
> > + case ICE_TIME_REF_FREQ_25_000:
> > + return "25 MHz";
> > + case ICE_TIME_REF_FREQ_122_880:
> > + return "122.88 MHz";
> > + case ICE_TIME_REF_FREQ_125_000:
> > + return "125 MHz";
> > + case ICE_TIME_REF_FREQ_153_600:
> > + return "153.6 MHz";
> > + case ICE_TIME_REF_FREQ_156_250:
> > + return "156.25 MHz";
> > + case ICE_TIME_REF_FREQ_245_760:
> > + return "245.76 MHz";
> > + default:
> > + return "Unknown";
> > + }
>
> Array lookup produces more optimized code than switch-case.
>
> static const char * const ice_clk_freqs[] = {
> [ICE_TIME_REF_FREQ_25_000] = "25 MHz",
> ...
> [NUM_ICE_TIME_REF_FREQ] = "Unknown",
> };
>
> static const char *ice_clk_freq_str(enum ice_time_ref_freq clk_freq)
> {
> return ice_clk_freqs[min(clk_freq, NUM_ICE_TIME_REF_FREQ)];
> }
I agree, but I'd like to avoid changing this now (in code move patch and
this patchset) if possible. I prepared another patchset, which is
refactoring and moving CGU related stuff into a separate file.
[...]
> > + * Clear all timestamps from the PHY quad block that is shared between the
> > + * internal PHYs on the E822 devices.
> > + */
> > +void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad)
> > +{
> > + ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M);
> > + ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL,
> > ~(u32)Q_REG_TS_CTRL_M);
>
> Is it intended to write the same register twice? Some reset sequence?
Yes, it's intended, E82X PHYs have multiple weird behaviours, especially
in PHY start sequence
[...]
Thanks,
Karol
